Altera Cyclone V GX FPGA Development Board Bedienungsanleitung PDF herunterladen (Seite 20)

2–12 Chapter 2: Board Components

FPGA Configuration

Cyclone V GX FPGA Development Board May 2013 Altera Corporation

Reference Manual

Table 2–5 lists the USB 2.0 PHY schematic signal names and their corresponding

Cyclone V GX device pin numbers.

Table 2–5. USB 2.0 PHY Schematic Signal Names and Functions (Part 1 of 2)

Board Reference

(U16)

Schematic

Signal Name

Cyclone V GX

Pin Number

I/O Standard Description

24M_XTALIN

— 3.3-V Crystal oscillator input

24M_XTALOUT

— 3.3-V Crystal oscillator output

FX2_D_N

— 3.3-V USB 2.0 PHY data

FX2_D_P

— 3.3-V USB 2.0 PHY data

FX2_FLAGA

— 3.3-V Slave FIFO output status

FX2_FLAGB

— 3.3-V Slave FIFO output status

FX2_FLAGC

— 3.3-V Slave FIFO output status

FX2_PA1

— 3.3-V USB 2.0 PHY port A interface

FX2_PA2

— 3.3-V USB 2.0 PHY port A interface

FX2_PA3

— 3.3-V USB 2.0 PHY port A interface

FX2_PA4

— 3.3-V USB 2.0 PHY port A interface

FX2_PA5

— 3.3-V USB 2.0 PHY port A interface

FX2_PA6

— 3.3-V USB 2.0 PHY port A interface

FX2_PA7

— 3.3-V USB 2.0 PHY port A interface

FX2_PB0

— 3.3-V USB 2.0 PHY port B interface

FX2_PB1

— 3.3-V USB 2.0 PHY port B interface

FX2_PB2

— 3.3-V USB 2.0 PHY port B interface

FX2_PB3

— 3.3-V USB 2.0 PHY port B interface

FX2_PB4

— 3.3-V USB 2.0 PHY port B interface

FX2_PB5

— 3.3-V USB 2.0 PHY port B interface

FX2_PB6

— 3.3-V USB 2.0 PHY port B interface

FX2_PB7

— 3.3-V USB 2.0 PHY port B interface

FX2_PD0