Altera Cyclone V GX FPGA Development Board Bedienungsanleitung PDF herunterladen (Seite 44)

2–36 Chapter 2: Board Components

Memory

Cyclone V GX FPGA Development Board May 2013 Altera Corporation

Reference Manual

DDR3A_CKE

AK18 1.5-V SSTL Class I Column address select

DDR3A_CLK_P

Y13 1.5-V SSTL Class I Differential output clock

DDR3A_CLK_N

AA14 1.5-V SSTL Class I Differential output clock

DDR3A_CSN

Y12 1.5-V SSTL Class I Chip select

DDR3A_DM2

AJ23 1.5-V SSTL Class I Write mask byte lane

DDR3A_DM3

AJ27 1.5-V SSTL Class I Write mask byte lane

DDR3A_DQ16

AE18 1.5-V SSTL Class I Data bus byte lane 2

DDR3A_DQ17

AD18 1.5-V SSTL Class I Data bus byte lane 2

DDR3A_DQ18

AJ20 1.5-V SSTL Class I Data bus byte lane 2

DDR3A_DQ19

AK22 1.5-V SSTL Class I Data bus byte lane 2

DDR3A_DQ20

AF19 1.5-V SSTL Class I Data bus byte lane 2

DDR3A_DQ21

AF18 1.5-V SSTL Class I Data bus byte lane 2

DDR3A_DQ22

AH21 1.5-V SSTL Class I Data bus byte lane 2

DDR3A_DQ23

AK23 1.5-V SSTL Class I Data bus byte lane 2

DDR3A_DQ24

AG19 1.5-V SSTL Class I Data bus byte lane 3

DDR3A_DQ25

AG18 1.5-V SSTL Class I Data bus byte lane 3

DDR3A_DQ26

AH24 1.5-V SSTL Class I Data bus byte lane 3

DDR3A_DQ27

AK25 1.5-V SSTL Class I Data bus byte lane 3

DDR3A_DQ28

AE20 1.5-V SSTL Class I Data bus byte lane 3

DDR3A_DQ29

AD19 1.5-V SSTL Class I Data bus byte lane 3

DDR3A_DQ30

AG24 1.5-V SSTL Class I Data bus byte lane 3

DDR3A_DQ31

AK26 1.5-V SSTL Class I Data bus byte lane 3

DDR3A_DQS_P2

Y20

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 2

DDR3A_DQS_N2

AA20

Differential 1.5-V SSTL

Class I

Data strobe N byte lane 2

DDR3A_DQS_P3

AB19

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 3

DDR3A_DQS_N3

AC19

Differential 1.5-V SSTL

Class I

Data strobe N byte lane 3

DDR3A_ODT

AH14 1.5-V SSTL Class I On-die termination enable

DDR3A_RASN

AG9 1.5-V SSTL Class I Row address select

DDR3A_RESETN

AK21 1.5-V SSTL Class I Reset

DDR3A_WEN

AK5 1.5-V SSTL Class I Write enable

DDR3A_ZQ2

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x8 (U23)

DDR3A_A0

AJ12 1.5-V SSTL Class I Address bus

DDR3A_A1

AK12 1.5-V SSTL Class I Address bus

DDR3A_A2

AH11 1.5-V SSTL Class I Address bus

Table 2–29. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Board Reference

Schematic

Signal Name

Cyclone V GX

Pin Number

I/O Standard Description

1 2 ... 39 40 41 42 43 44 45 46 47 48 49 ... 59 60

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