Altera Cyclone V GX FPGA Development Board Bedienungsanleitung PDF herunterladen (Seite 46)

2–38 Chapter 2: Board Components

Memory

Cyclone V GX FPGA Development Board May 2013 Altera Corporation

Reference Manual

Table 2–29 lists the DDR3B pin assignments, signal names, and functions. The signal

names and types are relative to the Cyclone V GX in terms of I/O setting and

direction.

Table 2–30. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board Reference

Schematic

Signal Name

Cyclone V GX

Pin Number

I/O Standard Description

DDR3 x16 (U6)

DDR3B_A0

Y30 1.5-V SSTL Class I Address bus

DDR3B_A1

R28 1.5-V SSTL Class I Address bus

DDR3B_A2

AA29 1.5-V SSTL Class I Address bus

DDR3B_A3

W29 1.5-V SSTL Class I Address bus

DDR3B_A4

U23 1.5-V SSTL Class I Address bus

DDR3B_A5

AA30 1.5-V SSTL Class I Address bus

DDR3B_A6

R23 1.5-V SSTL Class I Address bus

DDR3B_A7

AC30 1.5-V SSTL Class I Address bus

DDR3B_A8

T23 1.5-V SSTL Class I Address bus

DDR3B_A9

AB29 1.5-V SSTL Class I Address bus

DDR3B_A10

R30 1.5-V SSTL Class I Address bus

DDR3B_A11

R26 1.5-V SSTL Class I Address bus

DDR3B_A12

T25 1.5-V SSTL Class I Address bus

DDR3B_A13

AD29 1.5-V SSTL Class I Address bus

DDR3B_BA0

W30 1.5-V SSTL Class I Bank address bus

DDR3B_BA1

T24 1.5-V SSTL Class I Bank address bus

DDR3B_BA2

V30 1.5-V SSTL Class I Bank address bus

DDR3B_CASN

T30 1.5-V SSTL Class I Row address select

DDR3B_CKE

L28 1.5-V SSTL Class I Column address select

DDR3B_CLK_P

P22

Differential 1.5-V SSTL

Class I

Differential output clock

DDR3B_CLK_N

P23

Differential 1.5-V SSTL

Class I

Differential output clock

DDR3B_CSN

U29 1.5-V SSTL Class I Chip select

DDR3B_DM0

C29 1.5-V SSTL Class I Write mask byte lane

DDR3B_DM1

D29 1.5-V SSTL Class I Write mask byte lane

DDR3B_DQ0

D30 1.5-V SSTL Class I Data bus byte lane 0

DDR3B_DQ1

C30 1.5-V SSTL Class I Data bus byte lane 0

DDR3B_DQ2

F29 1.5-V SSTL Class I Data bus byte lane 0

DDR3B_DQ3

K22 1.5-V SSTL Class I Data bus byte lane 0

DDR3B_DQ4

E28 1.5-V SSTL Class I Data bus byte lane 0

DDR3B_DQ5

K21 1.5-V SSTL Class I Data bus byte lane 0

DDR3B_DQ6

G29 1.5-V SSTL Class I Data bus byte lane 0

DDR3B_DQ7

L23 1.5-V SSTL Class I Data bus byte lane 0

DDR3B_DQ8

J23 1.5-V SSTL Class I Data bus byte lane 1

1 2 ... 41 42 43 44 45 46 47 48 49 50 51 ... 59 60

Kommentare zu diesen Handbüchern

Keine Kommentare

Altera Cyclone V GX FPGA Development Board Bedienungsanleitung Seite 46

Kommentare zu diesen Handbüchern

Verwandte Produkte und Handbücher für Messgeräte Altera Cyclone V GX FPGA Development Board