Altera Avalon Verification IP Suite Bedienungsanleitung PDF herunterladen (Seite 91)

1–2 Chapter 1: Avalon-ST Source BFM

Functional Description

Avalon Verification IP Suite User Guide May 2011 Altera Corporation

Timing

The timing diagram shown in Figure 1–2 illustrates the timing for an Avalon-ST

Source BFM sending data to a sink. In the first instance the sink is not ready when the

source has data. In the second instance, the sink is ready but the source does not

initially have valid data.

1 The Avalon-ST BFM behaves differently depending on whether the sink’s

READY_LATENCY = 0

READY_LATENCY > 0

. When the ready latency is 0, the source

BFM holds its current transaction until the sink is ready. When the ready latency is

greater than 0, the BFM drives idles until the sink is ready, then it drives the

transaction. Figure 1–2 illustrates the timing when

READY_LATENCY = 0

Table 1–1 explains the annotations used in Figure 1–2.

Figure 1–2. Avalon-ST Source Sending Data to a Sink

CLK

ready

valid

data

D1 D2

src_dr

src_rdy

src_~rdy

src_rdy

idle

rl_1

Table 1–1. Key to Annotations in Figure 1–2

Symbol Description

idle

The idle time before a transactions. This time is set by the command

set_transaction_idles

rl_1

The response latency for the first source to sink transaction, which is three cycles. The

source gets this time using the

get_response_latency

command.

src_dr

Signals that the source is driving valid data. The event name is

signal_src_driving_transaction

src_rdy

Signals the source has received the assertion of

ready

from the sink. The event name is

signal_src_ready

Signals the first transaction is complete. The event name is

signal_src_transaction_complete

src_~rdy

Signals the source has received the deassertion of

ready

from the sink. The event name

signal_src_not_ready

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