Altera Avalon Verification IP Suite Bedienungsanleitung PDF herunterladen (Seite 48)

Chapter 3: Avalon-MM Slave BFM 3–5

Functional Description

May 2011 Altera Corporation Avalon Verification IP Suite User Guide

The timing diagram in Figure 3–3 illustrates the sequence of events for an Avalon-MM

Slave BFM receiving a write followed by a read when the

readdatavalid

signal is not

present.

Table 3–2 lists the annotations used in Figure 3–3.

Figure 3–3. Avalon-MM Slave Receiving Write and Read Commands with No readdatavalid Signal

CLK

read

write

waitrequest

byteenable[3:0]

writedata[31:0]

readdata

cr_1

wt_1

wt_2

cr_2

transaction5 transaction6

rc_1,

atc

Table 3–2. Key to Annotations in Figure 3–3 (Part 1 of 2)

Symbol Description

The initial command latency which is two cycles for transactions 1 and 2.

wt_1

The response wait time which is three cycles. The master gets this value using the

get_response_wait_time

command.

wt_2

The response wait time for the first read, which is two cycles. The slave sets this value using the

set_interface_wait_time

command.

waitrequest

is sampled #1 after the falling edge of

clk

rl_1

The response latency for the first read, which is zero cycles. The master gets this time using the

get_response_latency

command.

cr_1,

cr_2

Signals write and read commands. The event name is

signal_command_issued

1 2 ... 43 44 45 46 47 48 49 50 51 52 53 ... 177 178

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