Altera Avalon Verification IP Suite Bedienungsanleitung PDF herunterladen (Seite 27)

1–4 Chapter 1: Avalon-MM Master BFM

Functional Description

Avalon Verification IP Suite User Guide May 2011 Altera Corporation

The timing diagram in Figure 1–3 shows the sequence of events for an Avalon-MM

Master BFM driving a write followed by a read when the

readdatavalid

signal is not

present.

Table 1–2 lists the annotations used in Figure 1–3.

Figure 1–3. Avalon-MM Master Driving Write and Read Transactions with No readdatavalid Signal

CLK

read

write

waitrequest

byteenable[3:0]

writedata[31:0]

readdata

init

ci_1

wt_1

wt_2

ci_2

rc_1,

atc

transaction5 transaction6

idle

Table 1–2. Key to Annotations in Figure 1–3 (Part 1 of 2)

Symbol Description

init

The initial command latency, which is two cycles for transactions 1 and 2. This time is set by the API

command

set_command_init_latency

wt_1

The response wait time, which is three cycles. This time is determined by the number of cycles that the

waitrequest

signal is asserted by the slave.The program gets this value using the

get_response_wait_time

command.

wt_2

The response wait time for the first read, which is two cycles. This time is determined by the number of

cycles that the

waitrequest

signal is asserted by the slave.The program gets this value using the

get_response_wait_time

command.

waitrequest

is always sampled #1 after the falling edge of

clk

idle

The idle time after a transaction. This time is set by the command

set_command_idle.

1 2 ... 22 23 24 25 26 27 28 29 30 31 32 ... 177 178

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