Altera 10-Gbps Ethernet MAC MegaCore Function Bedienungsanleitung Seite 95
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February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
8. Registers
This section defines the MAC registers. The statistics collected on the transmit and
receive datapaths are categorized as good, error, or invalid frames.
■ Good frame—Error-free frames with a valid frame length.
■ Error frame—Frames that contain errors or with an invalid frame length.
■ Invalid frame—Frames that are not addressed to the MAC. It may or may not
contain error within the frame or have an invalid frame length. The MAC drops
invalid frames.
When you select the MAC Rx only variation, the register offsets from 0x000 to 0x3FFF
are available for Rx status and configuration registers. Similarly, when you select the
MAC TX only variation, the register offsets from 0x4000 to 0x7FFF are available for TX
status and configuration registers. All status and configuration registers are as
defined in Table 8–2 on page 8–2.
c Altera recommends accessing only the available register spaces in the MAC Rx only
variation or the MAC TX only variation. Accessing unavailable register spaces may
cause the MAC to lock the Avalon-MM bus.
1 Altera has updated all register address for the 10GbE MAC IP core as part of register
map expansion to accommodate new registers. Table 8–1 summarizes the changes.
.
Table 8–1. Summary of Register Address Expansion
Component Name
Previous Address Range
(ACDS Version 10.0, 10.1)
New Address Range
(ACDS Version 11.0 Onwards)
RX Datapath
RX Packet Transfer 0x000:0x00F 0x000:0x0FF
RX Pad/CRC Remover 0x010:0x01F 0x100:0x1FF
RX CRC Checker 0x020:0x0FF 0x200:0x2FF
RX Packet Overflow 0x180:0x1FF 0x300:0x3FF
RX Preamble Control — 0x400:0x4FF
RX Lane Decoder — 0x500:0x1FFF
RX Frame Decoder 0x100:0x17F 0x2000:0x2FFF
RX Statistics Counters 0x200:0x3FF 0x3000:0x3FFF
TX Datapath
TX Packet Transfer 0x400:0x40F 0x4000:0x40FF
TX Pad Inserter 0x410:0x41F 0x4100:0x41FF
TX CRC Inserter 0x420:0x45F 0x4200:0x42FF
TX Packet Underflow 0x580:0x5FF 0x4300:0x43FF
TX Preamble Control — 0x4400:0x44FF
TX Pause Frame Control and
Generator
0x460:0x47F 0x4500:0x45FF
- User Guide 1
- Contents 3
- Contents iv 4
- Chapter 8. Registers 5
- Chapter 9. Interface Signals 5
- 1. About This IP Core 7
- 1.2. Release Information 8
- 1.3. Device Family Support 9
- 1.4. IP Core Verification 10
- ■ Timestamping is enabled 12
- ■ ptp_1step is disabled 12
- 2.2. Design Flows 14
- 2.3.2. Simulate the IP Core 15
- 2.4.1. Specify Parameters 16
- 2.4.3. Simulate the System 17
- [1] register bit to 1 18
- 3. 10GbE MAC Design Examples 19
- 3.2.0.2. Base Addresses 22
- Table 3–5 on page 3–10 23
- Creating a New 10GbE Design 24
- 3.6. 10GbE Testbenches 26
- 3.6.3. 10GbE Testbench Files 27
- 10GbE Testbenches 28
- Notes to Table 3–6: 36
- 4.1. Software Requirements 39
- Altera FPGA 40
- Design Example 40
- 4.2.1. Base Addresses 41
- Figure 4–3. Testbench 43
- The <ip 44
- Simulator 45
- 5.2.2. Base Addresses 49
- 1G/10GbE Design Example Files 50
- 5.5. 1G/10GbE Testbench 51
- Testbench 52
- 1G/10GbE Testbench 53
- 5.5.4.2. Backplane-KR Mode 55
- 6.2.1. Base Addresses 62
- ModelSim Simulator 66
- 7. Functional Description 68
- Architecture 69
- 7.2. Interfaces 70
- 7.2.2. SDR XGMII 71
- 7.2.3. GMII 71
- 7.2.4. MII 71
- 7.3. Frame Types 72
- 7.4. Transmit Datapath 72
- 7.4.2. Address Insertion 73
- Note to Figure 7–5: 74
- 7.4.4. XGMII Encapsulation 75
- 7.4.6. SDR XGMII Transmission 76
- Figure 7–7. Endian Conversion 77
- 7.5. Receive Datapath 78
- 7.5.4. Address Checking 79
- 7.5.5. Frame Type Checking 79
- 7.5.6. Length Checking 80
- 7.5.7. CRC-32 and Pad Removal 81
- 7.5.8. Overflow Handling 82
- Congestion and Flow Control 83
- 7.7.2.1. PFC Frame Reception 86
- Figure 7–11. Fault Signaling 87
- 7.9. IEEE 1588v2 88
- IEEE 1588v2 89
- 7.9.1. Architecture 90
- 7.9.2. Transmit Datapath 91
- 7.9.3. Receive Datapath 92
- 7.9.4. Frame Format 92
- MAC Header 93
- Note to Figure 7–16: 94
- 8. Registers 95
- 8.1. MAC Registers 96
- 0x0C1. Bits 4 to 31 are 98
- 0x0C3. Bits 4 to 31 are 98
- Register Name Access 100
- Bits 4 to 31 are reserved 101
- register 111
- Name R/W Description 112
- 8.3. Register Initialization 113
- 8–20 Chapter 8: Registers 114
- Register Initialization 114
- Chapter 8: Registers 8–21 115
- 8–22 Chapter 8: Registers 116
- Chapter 8: Registers 8–23 117
- 8–24 Chapter 8: Registers 118
- Chapter 8: Registers 8–25 119
- 9. Interface Signals 120
- Note to Table 9–1: 121
- Note to Figure 9–2: 123
- Note to Figure 9–3: 123
- Notes to Figure 9–4: 124
- Note to Figure 9–5: 125
- 9.0.3. SDR XGMII 127
- Note to Figure 9–7: 128
- Note to Figure 9–8: 129
- 9.0.4. GMII Signals 130
- 9.0.5. MII Signals 130
- Note to Table 9–8: 136
- Note to Table 9–9: 139
- 1588v2 feature 142
- 10. Design Considerations 150
- 10GbE MAC XAUI/10G BASE-R PHY 151
- Reconfiguration Controller 151
- A. Frame Format 153
- Figure A–2. VLAN Frame Format 154
- A.3. Pause Frame 155
- Figure A–5. PFC Frame Format 156
- B. Time-of-Day (ToD) Clock 157
- B.4. Parameter Setting 158
- ■ Bits 20 to 31: Not used 160
- B.6.1. Adjusting ToD’s Drift 161
- C. Packet Classifier 162
- Classifier 163
- D. ToD Synchronizer 166
- D.2. Block Diagram 167
- D.4. ToD Synchronizer Signals 169
- Additional Information 171
- Info–2 Additional Information 172
- Document Revision History 172
- Additional Information Info–3 173
- How to Contact Altera 174
- Typographic Conventions 174
- Additional Information Info–5 175
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