Altera 10-Gbps Ethernet MAC MegaCore Function Bedienungsanleitung Seite 50
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Chapter 5: 1G/10GbE MAC Design Example 5–5
1G/10GbE Design Example Files
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
1 This design example uses a 19-bit width address bus to access the base address of
components other than the MAC.
f For more information about the 10GBASE-KR, refer to the 10GBASE-KR PHY IP Core
chapter in the Altera Transceiver PHY IP Core User Guide.
5.3. 1G/10GbE Design Example Files
Figure 5–3 shows the directory structure for the 1G/10GbE design examples and
testbenches.
Table 5–3 lists the files in the
..\altera_eth_10g_mac_base_kr directory.
10GBASE-KR Channel 0 0x80000
10GBASE-KR Channel 1 0x80800
Configure Reconfiguration Channel 0 0x80400
Configure Reconfiguration Channel 1 0x80500
RX FIFO (Avalon-ST Single-Clock FIFO) Channel 0 0x10400
TX FIFO (Avalon-ST Single-Clock FIFO) Channel 0 0x10600
RX FIFO (Avalon-ST Single-Clock FIFO) Channel 1 0x30400
TX FIFO (Avalon-ST Single-Clock FIFO) Channel 1 0x30600
Table 5–2. Base Addresses of 1G/10GbE Design Example Components
Component Base Address
Figure 5–3. 1G/10GbE Design Example Folders
Table 5–3. 1G/10GbE Design Example Files
File Name Description
altera_eth_10g_mac_base_kr_top.v
The top-level entity file of the design example for
verification in hardware.
altera_eth_10g_mac_base_kr_top.sdc
The Quartus II SDC constraint file for use with
the TimeQuest timing analyzer.
setup_proj.tcl
A Tcl script that creates a new Quartus II project
and sets up the project environment for your
design example.
altera_eth_10g_mac_base_kr.qsys
A Qsys file for the 1G/10GbE MAC and 10G
BASE-KR PHY design example with the
Quartus II software targeting the Stratix V device.
reconfig.v
A top-level entity file for the transceiver
reconfiguration controller IP.
<ip_lib>/ethernet/altera_eth_10g_design_example
altera_eth_10g_mac_base_kr
testbench
reconfig
- User Guide 1
- Contents 3
- Contents iv 4
- Chapter 8. Registers 5
- Chapter 9. Interface Signals 5
- 1. About This IP Core 7
- 1.2. Release Information 8
- 1.3. Device Family Support 9
- 1.4. IP Core Verification 10
- ■ Timestamping is enabled 12
- ■ ptp_1step is disabled 12
- 2.2. Design Flows 14
- 2.3.2. Simulate the IP Core 15
- 2.4.1. Specify Parameters 16
- 2.4.3. Simulate the System 17
- [1] register bit to 1 18
- 3. 10GbE MAC Design Examples 19
- 3.2.0.2. Base Addresses 22
- Table 3–5 on page 3–10 23
- Creating a New 10GbE Design 24
- 3.6. 10GbE Testbenches 26
- 3.6.3. 10GbE Testbench Files 27
- 10GbE Testbenches 28
- Notes to Table 3–6: 36
- 4.1. Software Requirements 39
- Altera FPGA 40
- Design Example 40
- 4.2.1. Base Addresses 41
- Figure 4–3. Testbench 43
- The <ip 44
- Simulator 45
- 5.2.2. Base Addresses 49
- 1G/10GbE Design Example Files 50
- 5.5. 1G/10GbE Testbench 51
- Testbench 52
- 1G/10GbE Testbench 53
- 5.5.4.2. Backplane-KR Mode 55
- 6.2.1. Base Addresses 62
- ModelSim Simulator 66
- 7. Functional Description 68
- Architecture 69
- 7.2. Interfaces 70
- 7.2.2. SDR XGMII 71
- 7.2.3. GMII 71
- 7.2.4. MII 71
- 7.3. Frame Types 72
- 7.4. Transmit Datapath 72
- 7.4.2. Address Insertion 73
- Note to Figure 7–5: 74
- 7.4.4. XGMII Encapsulation 75
- 7.4.6. SDR XGMII Transmission 76
- Figure 7–7. Endian Conversion 77
- 7.5. Receive Datapath 78
- 7.5.4. Address Checking 79
- 7.5.5. Frame Type Checking 79
- 7.5.6. Length Checking 80
- 7.5.7. CRC-32 and Pad Removal 81
- 7.5.8. Overflow Handling 82
- Congestion and Flow Control 83
- 7.7.2.1. PFC Frame Reception 86
- Figure 7–11. Fault Signaling 87
- 7.9. IEEE 1588v2 88
- IEEE 1588v2 89
- 7.9.1. Architecture 90
- 7.9.2. Transmit Datapath 91
- 7.9.3. Receive Datapath 92
- 7.9.4. Frame Format 92
- MAC Header 93
- Note to Figure 7–16: 94
- 8. Registers 95
- 8.1. MAC Registers 96
- 0x0C1. Bits 4 to 31 are 98
- 0x0C3. Bits 4 to 31 are 98
- Register Name Access 100
- Bits 4 to 31 are reserved 101
- register 111
- Name R/W Description 112
- 8.3. Register Initialization 113
- 8–20 Chapter 8: Registers 114
- Register Initialization 114
- Chapter 8: Registers 8–21 115
- 8–22 Chapter 8: Registers 116
- Chapter 8: Registers 8–23 117
- 8–24 Chapter 8: Registers 118
- Chapter 8: Registers 8–25 119
- 9. Interface Signals 120
- Note to Table 9–1: 121
- Note to Figure 9–2: 123
- Note to Figure 9–3: 123
- Notes to Figure 9–4: 124
- Note to Figure 9–5: 125
- 9.0.3. SDR XGMII 127
- Note to Figure 9–7: 128
- Note to Figure 9–8: 129
- 9.0.4. GMII Signals 130
- 9.0.5. MII Signals 130
- Note to Table 9–8: 136
- Note to Table 9–9: 139
- 1588v2 feature 142
- 10. Design Considerations 150
- 10GbE MAC XAUI/10G BASE-R PHY 151
- Reconfiguration Controller 151
- A. Frame Format 153
- Figure A–2. VLAN Frame Format 154
- A.3. Pause Frame 155
- Figure A–5. PFC Frame Format 156
- B. Time-of-Day (ToD) Clock 157
- B.4. Parameter Setting 158
- ■ Bits 20 to 31: Not used 160
- B.6.1. Adjusting ToD’s Drift 161
- C. Packet Classifier 162
- Classifier 163
- D. ToD Synchronizer 166
- D.2. Block Diagram 167
- D.4. ToD Synchronizer Signals 169
- Additional Information 171
- Info–2 Additional Information 172
- Document Revision History 172
- Additional Information Info–3 173
- How to Contact Altera 174
- Typographic Conventions 174
- Additional Information Info–5 175
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