Altera SerialLite II IP Core Bedienungsanleitung Seite 67
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Chapter 4: Functional Description 4–13
Clocks and Data Rates
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
Arria V, Cyclone V, and Stratix V Transceiver Clocking
For Arria V, Cyclone V, and Stratix V configurations, you must integrate the
transceiver to the SerialLite II MegaCore function manually.
When you configure the transceiver to work in more than 1 lane per SerialLite II
instance, the
tx_clkout(0)
signal from the TX channel (PHY IP) must drive the
SerialLite II input clock (
tx_coreclk
) and the input port (
tx_coreclkin
) of all TX
channels (PHY IP). Similarly, if your design requires more than 1 RX channel per
SerialLite II instance, the
rx_clkout(0)
from the RX channel (PHY IP) must drive the
SerialLite II input clock (
rx_coreclk
) and the input port (
rx_coreclkin
) of all RX
channels (PHY IP).
SerialLite II MegaCore Pin-Out Diagrams
This section shows pin-out diagrams for the SerialLite II MegaCore function. The
following diagrams are included:
■ Arria II GX/Stratix IV PHY Layer
■ Transmitter Link Layer
■ Receiver Layer With No FIFO
■ Receiver Link Layer With FIFO
Figure 4–12. Full Featured Clock Structure for 5G Symmetrical With TSIZE = 2
XCVR
TX Core
n-bit
n-bit
RX Core
n-bit
Atlantic
#n SLITE2
High
Speed
Links
#m SLITE2
High
Speed
Links
Atlantic
Atlantic
Atlantic
Regular
Priority
Priority
Regular
PComp_
FIFO_0
Byte
serializer
Byte
serializer
PComp_
FIFO_n-1
Byte
deserializer
Byte
deserializer
n
-
b
i
t
rxrdp_clk
rxhpp_clk
txhpp_clk
txrdp_clk
tx_coreclk
rcvd_clkn-1
mreset_n
Reset Sync
tx_coreclock
rcvd_clk_out[n-1:0]
ATLFIFO
ATLFIFO
ATLFIFO
ATLFIFO
tx_coreclock
Word Aligner (&
Training Pattern
Detection),
[Link State
Machine]
Training
Generator [Link
State Machine]
trefclk
TXPLL
tx_coreclock
tx_coreclock
tx_coreclock
tx_coreclock
RM_
FIFO_0
RM_
FIFO_n-1
slite2_top
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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