Altera SerialLite II IP Core Bedienungsanleitung Seite 102
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5–16 Chapter 5: Testbench
Example Testbench – Verilog HDL
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
Pin_mon Tasks - Verilog HDL
Table 5–11 shows the function of the
pin_mon
tasks.
Clock and Reset Generator
The DUT and the SISTER use a common clock, with the frequency set by the
MegaWizard Plug-In Manager.
There is one master reset signal (
reset_n
) that resets all the logic in the demonstration
testbench (DUT, SISTER(s), AGENs, AMONs and status monitors).
1 Ensure
reset_n
to the MegaCore function starts high at
Time=0
, and then goes low for
proper reset of the simulation model. Some simulators do not detect the transition if
reset_n
is asserted low at
T=0
.
To allow for easy modification, the reset section of the testbench is marked by
start–end comment tags:
SERIALLITE2_TB_RESET_START
SERIALLITE2_TB_RESET_END
1 The clock and reset utilities are included in the testbench top-level file.
Custom PHY IP Core
The DUT and the SISTER use an external transceiver for Arria V and Stratix V
configurations. You are required to separately instantiate the Custom PHY IP core
using the MegaWizard Plug-In Manager.
Example Testbench – Verilog HDL
To allow for easy modification of the demonstration testbench, its main section is
marked by start–end tags:
//SERIALLITE2_TB_MAIN_START
//SERIALLITE2_TB_MAIN_END
Because there is no Atlantic to Atlantic score-boarding, the demonstration testbench
focuses on passing error-free data rather than errored data. Any error condition that
involves dropped or errored packets, must be handled in the testbench by setting
proper expectations.
Table 5–11. pin_mon Tasks
Task Function
on
This task enables monitoring (the
en
input pin must also be set high to enable
monitoring).
off
This task disables monitoring (regardless of the value of the
en
input pin).
verbose_on
This task enables the display of verbose messages.
verbose_off
This task disables the display of verbose messages.
set_expect (bit_value)
This task sets the expected pin value.
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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