Altera SerialLite II IP Core Bedienungsanleitung Seite 51
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3–28 Chapter 3: Parameter Settings
Error Handling
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
Error Handling
The SerialLite II MegaCore function does error checking and has an interface to view
local errors. The errors are categorized, and the effect of an error depends on the type
of error that occurs.
The SerialLite II MegaCore function has three error types:
■ Data error
■ Link error
■ Catastrophic error
The causes and results of these errors are summarized in Table 3–12.
reconfig_fromgxb
O
The
reconfig_fromgxb
output signal is driven to an external dynamic
reconfiguration block. The width of this bus depends on the number of lanes (it may
require multiple transceiver QUAD blocks), and the device family (for Arria II GX and
Stratix IV, the bus is wider due to offset cancelation support).
This signal identifies the transceiver channel whose settings are being transmitted to
the dynamic reconfiguration. This signal must be connected as described in the
Arria II GX Device Handbook or the Stratix IV Device Handbook if the external dynamic
reconfiguration block is used. Otherwise, leave this signal unconnected.
For Arria II GX and Stratix IV, you must use the dynamic reconfiguration block because
they require offset cancelation.
gxb_powerdown
I
gxb_powerdown
resets and powers down all circuits in the transceiver block. This
signal does not affect the refclk buffers and reference clock lines.
All the gxb_powerdown input signals of cores placed in the same quad should be tied
together. The
gxb_powerdown
signal should be tied low or should remain asserted for
at least 2 ms whenever it is asserted.
Table 3–11. ALTGX Support Signals
Signal
I/O Description
Table 3–12. Error Summary (Part 1 of 2)
Error Type Cause Action
Catastrophic
■ LSM cannot reverse polarity
■ LSM cannot reorder lanes
SerialLite II enters
nonrecoverable state
Link
■ Eight consecutive {|TS1|} sequences
received in all lanes simultaneously
■ Loss of character alignment
■ Loss of lane alignment
■ Loss of characters from
underflow/overflow
■ Data error threshold exceeded
■ Retry-on-error timer expired three
times
Trigger link initialization
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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