Altera SerialLite II IP Core Handbücher

Bedienungsanleitungen und Benutzerhandbücher für Messgeräte Altera SerialLite II IP Core.
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Altera SerialLite II IP Core Bedienungsanleitung (110 Seiten)

Marke: Altera | Kategorie: Messgeräte | Größe: 2.07 MB |

Inhaltsverzeichnis

User Guide

Contents

Chapter 5. Testbench

Release Information

Device Family Support

Features

General Description

(EP2GX90FF1508C3)

Notes to Table 1–3:

Installation and Licensing

OpenCore Plus Evaluation

Simulate with Testbench

Design Flow

Parameterize

Set Up Simulation

Generate Files

Simulate the Design

Instantiate the MegaCore

Specify Constraints

Compile and Program

3. Parameter Settings

Link Consistency

Physical Layer Configuration

Transfer size

Reference Clock Frequency

Port Type

Notes to Figure 3–3:

Note to Figure 3–4:

Note to Figure 3–5:

Notes to Figure 3–6:

Self Synchronized Link Up

Number of Lanes

Scramble

De-Scramble

Broadcast Mode

Clock Compensation

Link Layer Configuration

Retry-on-error Disabled

Retry-on-error Enabled

Segment Size

Retry-on-error

Retry-on-error Responses

Flow Control

Notes to Figure 3–12:

Notes to Table 3–6:

Transmit/Receive FIFO Buffers

FIFO Buffer Size

FIFO Buffer Structure

16-Bit Versus 32-Bit CRC

Transceiver Configuration

Transmitter Buffer Power (V

Equalizer Control Settings

Bandwidth Mode

Starting Channel number

ALTGX Support Signals

Error Handling

Optimizing the Implementation

Feature Selection

Running Different Seeds

Limiting Fanout

Floorplanning

Minimizing Memory Utilization

4. Functional Description

Atlantic Interface

High-Speed Serial Interface

Clocks and Data Rates

External Clock Modes

SerialLite II Deskew Support

Note to Figure 4–6:

Note to Figure 4–7:

Note to Figure 4–8:

Note to Figure 4–9:

Note to Figure 4–10:

Note to Figure 4–11:

Note to Figure 4–14:

Initialization and Restart

Multiple Core Configuration

Compilation

Testbench

Simulation Support

Notes to Table 4–5:

Notes to Table 4–6:

Notes to Table 4–7:

Notes to Table 4–8:

Notes to Table 4–9:

Note to Table 4–10:

MegaCore Verification

5. Testbench

Testbench Specifications

Notes to Figure 5–1:

5–4 Chapter 5: Testbench

Simulation Flow

Running a Simulation

Chapter 5: Testbench 5–7

Testbench Time-Out

Verilog HDL

5–10 Chapter 5: Testbench

Chapter 5: Testbench 5–11

Chapter 5: Testbench 5–13

5–14 Chapter 5: Testbench

100

Status Monitors (pin_mon)

101

Pin_mon Tasks - Verilog HDL

102

Chapter 5: Testbench 5–17

103

5–18 Chapter 5: Testbench

104

Chapter 5: Testbench 5–19

105

5–20 Chapter 5: Testbench

106

Chapter 5: Testbench 5–21

107

Additional Information

108

Typographic Conventions

109

Visual Cue Meaning

110

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Altera SerialLite II IP Core Handbücher

Altera SerialLite II IP Core Bedienungsanleitung (110 Seiten)

Inhaltsverzeichnis

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