Altera SerialLite II IP Core Bedienungsanleitung Seite 31
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3–8 Chapter 3: Parameter Settings
Physical Layer Configuration
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
2. Wait for the
rx_freqlocked
signal (
stat_rr_freqlock
) to be asserted, which
happens when the ALTGX megafunction locks onto the serial stream; 5 ms or less
is normal.
3. The Rx digital reset needs to complete; this reset normally takes one million
internal
tx_coreclock
cycles after
rx_freqlocked
is asserted. The
stat_tc_rst_done
signal is asserted to indicate that the reset sequence has been
completed.
1 The normal time values are much shorter in simulation (For example, using
the IP Functional Simulation Model), but not in gate-level simulation. Gate-
level simulation uses the hardware equivalent times.
As you have full visibility of the above signals (via the SignalTap
®
II logic analyzer
and the port list), you should characterize the timing of these signals to set up the size
of your
ctrl_tc_force_train
counter. The MegaCore function also has a reset done
status signal (
stat_tc_rst_done
) that can be useful for measurements. The following
MegaCore function status output signals correspond to each step above:
■
stat_tc_pll_locked
■
stat_rr_freqlock
■
stat_tc_rst_done
(to see when
rx_digitalreset
has been negated).
After the reset controller completes, the MegaCore function waits for the transceiver
byte aligner to detect and align the control (k28.5) character in the training sequence.
Once the transceiver detects this character, the count starts at every k28.5 that is
received (basically, counting every training sequence). Once 64 error-free training
sequences have been received, the MegaCore function reports linkup. Any errors (for
example, disparity or 8B/10B errors) that are received reset the count, and the
MegaCore function continues to wait until 64 error-free training patterns are received.
1 The self-synchronizing LSM also locks onto the clock compensation sequence. As
turning on the Clock Compensation option allows the receiver to automatically
relock if the link goes down, the transmitter is not required to assert
ctrl_tc_force_train
to retrain the link (which may be impossible in a unidirectional
link because the transmitter does not necessarily detect that the receiver has lost the
link).
Number of Lanes
Because each lane operates at the bit rate, you can increase the bandwidth by adding
lanes. Adding lanes—up to a maximum of 16—is a simple way to scale the link
during system design. If adding a lane provides more bandwidth than needed, you
can reduce the system clock rate, thereby mitigating possible high-speed design issues
and making it easier to meet performance.
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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