Altera Remote Update IP Core Bedienungsanleitung

Altera Remote Update IP Core User Guide2015.04.07UG-31005SubscribeSend FeedbackThe Altera Remote Update IP core implements a remote system update usin

Remote System Configuration ComponentsTable 2: Remote System Configuration Components in Arria 10 DevicesComponents DetailsPage mode featureThe dedica

Components DetailsRemote configurationregistersThe remote configuration registers keep track of page addresses and the causeof configuration errors. Y

Name Port Required? Descriptionwrite_paramInputNo Write signal for parameter specified in param[] andwith value specified in data_in[].Signal indicati

Name Port Required? Descriptionreset_timerInputNo Reset signal for watchdog timer.Signal indicating the internal watchdog timer shouldbe reset. Unlike

Name Port Required? Descriptiondata_out[]OutputNo Data output when reading parameters.This bus holds read parameter data from the remoteupdate block.

Bit Parameter Width Comments010 Watchdog Timeout Value 12 —011 Watchdog Enable 1 —100 Page Select 32For the Quartus II software version 14.0 and onwar

Remote Configuration ModeFigure 9: Remote Configuration ModePower UpSet Control Registerand ReconfigureReload a Different ApplicationReload a Differen

Components DetailsWatchdog timerA watchdog timer is a circuit that determines the functionality ofanother mechanism. The watchdog timer functions like

GUI Name Legal Value in GUI DescriptionAdd support for writingconfiguration parameters—Enable this if you need to write configurationparameters.Enable

Name Port Required?Descriptionwrite_paramInputNo Write signal for parameter specified in param[]and with value specified in data_in[].Signal indicatin

Figure 2: IP Core Installation Pathacdsquartus - Contains the Quartus II softwareip - Contains the Altera IP Library and third-party IP coresaltera -

Name Port Required?Descriptiondata_in[]InputNo Data input for writing parameter data into theremote update block. Input bus for parameterdata.For some

Name Port Required?DescriptionresetInputYes This is an active high signal. Asserting this signalhigh will reset the IP core.Asynchronous reset input t

Name Port Required?Descriptionasmi_busyInputNo Input from the altasmi_parallel component.Available when the check_app_pof parameter isset to true.A lo

Name Port Required?Descriptionasmi_addrOutputNo Address signal to altasmi_parallelcomponent.Available when the check_app_pof parameter isset to TRUE.

Bit Parameter Width Comments010 Watchdog Timeout Value 12 —011 Watchdog Enable 1 —100 Page Select 24 or 32For the Quartus II software version 13.1 and

Remote System Configuration ModeCyclone IV devices support remote configuration mode only.Remote Configuration ModeFigure 10: Remote Configuration Mod

Components DetailsFactory configurationFactory configuration is the default configuration setup.In remote configuration mode, the factory configuratio

Components DetailsWatchdog timerA watchdog timer is a circuit that determines the functionality ofanother mechanism. The watchdog timer functions like

GUI Name Legal Value in GUI DescriptionWhich configurationdevice will you be using?• EPCS device• EPCQ deviceChoose the configuration device that you

Name Port Required?Descriptionwrite_paramInputNo Write signal for parameter specified in param[]and with value specified in data_in[].Signal indicatin

Figure 3: Quartus II IP CatalogSearch and filter IP for your target deviceDouble-click to customize, right-click for detailed informationNote: The IP

Name Port Required?Descriptiondata_in[]InputNo Data input for writing parameter data into theremote update block. Input bus for parameterdata.For some

Name Port Required?Descriptionread_sourceInputYes Specifies whether a parameter value is read fromthe current or a previous state.This 2-bit port spec

Name Port Required?Descriptiondata_out[]OutputNo Data output when reading parameters.This bus holds read parameter data from theremote update block. T

Name Port Required?Descriptionasmi_dataoutInputNo Input from the altasmi_parallel component.Available when the check_app_pof parameter isset to true.T

Name Port Required?Descriptionasmi_rdenOutputNo Read enable signal to altasmi_parallelcomponent.Available when the check_app_pof parameter isset to TR

Bit Parameter Width Comments100 Boot Address —For the Quartus II software version 13.1 andonwards:• Width of 29 or 32 when reading the boot address.•

read_paramwrite_paramread_source param Remote Update Operation data_outwidth(bits)MSM Mode1 0 [00] [000] Master State Machine Current State Mode(Read

read_paramwrite_paramread_source param Remote Update Operation data_outwidth(bits)MSM Mode0 1 [00] [011]Write the watchdog enable bit.All parameters c

Figure 11: State RegisterApplication 1ConfigurationApplication 2ConfigurationFactoryConfigurationConfigured the Application 1from Factory Switched to

a. Browse to the folder in which you unzipped the files and open the Application_Image.qpf.b. Click Yes in the message box "Do you want to overwr

Figure 4: IP Parameter EditorsView IP portand parameter detailsApply preset parameters forspecific applicationsSpecify your IP variation nameand targe

Table 15: Document Revision HistoryDate Version ChangesApril 2015 2015.04.07 Added design example link.January 2015 2015.01.23 Updated Arria 10 remote

Date Version ChangesJuly 2013 2013.07.12• Updated Watchdog Timer to include the watchdogreset_time requirement to ensure the validity of theapplicatio

Date Version ChangesJuly 2013 2013.07.12• Added Cyclone III and Cyclone IV Devices RemoteUpdate Operation.• Updated Input Ports to include Arria V and

Date Version ChangesMay 2007 2.3Updated for Quartus II software v7.1, including:• Updated to include support for Arria GX devices.• Updated to include

7. To generate an HDL instantiation template that you can copy and paste into your text editor, clickGenerate > HDL Example.8. Click Finish. The pa

reads only the instance name and ignores entity names in paths that specify both entity andinstance names. The upgrade process preserves the original

Figure 6: Upgrading IP CoresRuns “Auto Upgrade” on all supported outdated coresOpens editor for manual IP upgrade “Auto Upgrade”supportedUpgrade requi

Related InformationAltera IP Release NotesSimulating Altera IP Cores in other EDA ToolsThe Quartus II software supports RTL and gate-level design simu

models only for simulation and not for synthesis or any other purposes. Using these models forsynthesis creates a nonfunctional design.Related Informa