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Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3
34
SystemVerilog Master BFM
Master Assertions
April 2014
Master Assertions
The master BFM performs protocol error checking using built-in assertions.
Note
The built-in BFM assertions are independent of programming language and simulator.
By default, all built-in assertions are enabled in the master BFM. To globally disable them in the
master BFM, use the set_config() command as shown in Example 3-2.
Example 3-2. Master BFM Disable All Assertions
set_config(AXI4STREAM_CONFIG_ENABLE_ALL_ASSERTIONS,0)
Alternatively, you can disable individual built-in assertions by using a sequence of get_config()
and set_config() commands on the respective assertion. Example 3-3 shows how to disable
assertion checking for the TLAST signal changing between the TVALID and TREADY
handshake signals.
Example 3-3. Master BFM Individual Assertion Enable/Disable
// Define a local bit vector to hold the value of the assertion bit vector
bit [255:0] config_assert_bitvector;
// Get the current value of the assertion bit vector
config_assert_bitvector =
bfm.get_config(AXI4STREAM_CONFIG_ENABLE_ASSERTION);
// Assign the AXI4STREAM_TLAST_CHANGED_BEFORE_TREADY assertion bit to 0
config_assert_bitvector[AXI4STREAM_TLAST_CHANGED_BEFORE_TREADY] = 0;
// Set the new value of the assertion bit vector
bfm.set_config(AXI4STREAM_CONFIG_ENABLE_ASSERTION,
config_assert_bitvector);
Note
Do not confuse the AXI4STREAM_CONFIG_ENABLE_ASSERTION bit vector with
the AXI4STREAM_CONFIG_ENABLE_ALL_ASSERTIONS global enable/disable.
To re-enable the AXI4STREAM_TLAST_CHANGED_BEFORE_TREADY assertion, follow
the code sequence in Example 3-3 and assign the assertion enable within the
AXI4STREAM_CONFIG_ENABLE_ASSERTION bit vector to 1.
For a complete listing of AXI4-Stream assertions, refer to “Assertions” on page 205.
- AMBA AXI4-Stream User Guide 1
- Table of Contents 3
- List of Examples 10
- List of Figures 11
- List of Tables 12
- About This User Guide 13
- Supported Simulators 13
- Simulator GCC Requirements 14
- Chapter 1 17
- Mentor VIP Altera Edition 17
- What Is a Transaction? 18
- AXI4-Stream Transactions 19
- Chapter 2 21
- SystemVerilog API Overview 21
- Configuration 22
- Creating Transactions 22
- Transaction Record 23
- Executing Transactions 26
- Waiting Events 27
- Access Transaction Record 27
- Operation Mode 28
- Handshake Delay 29
- Transfer Done 30
- Transaction Done 30
- Chapter 3 31
- SystemVerilog Master BFM 31
- Master BFM Configuration 32
- Master Assertions 34
- SystemVerilog Master API 35
- Returns 36
- Arguments config_name 37
- Chapter 4 43
- SystemVerilog Slave BFM 43
- SystemVerilog Slave API 47
- Chapter 5 55
- SystemVerilog Monitor BFM 55
- SystemVerilog Monitor API 59
- Chapter 6 67
- SystemVerilog Tutorials 67
- Chapter 7 75
- VHDL API Overview 75
- Test Program VHDL 76
- Chapter 8 87
- VHDL Master BFM API 91
- April 2014 100
- Prototype 118
- Arguments 118
- VHDL Master BFM 122
- VHDL Slave BFM 123
- Chapter 9 123
- Slave BFM Configuration 124
- Slave Assertions 125
- VHDL Slave BFM API 126
- Chapter 10 157
- VHDL Monitor BFM 157
- Monitor BFM Configuration 158
- Monitor Assertions 159
- VHDL Monitor BFM API 161
- Chapter 11 181
- VHDL Tutorials 181
- Master BFM Test Program 182
- Verifying a Master DUT 185
- Chapter 12 189
- Running the Qsys Tool 193
- Running a Simulation 195
- ModelSim Simulation 196
- Editing the modelsim.ini File 199
- Questa Simulation 200
- Cadence IES Simulation 200
- Synopsys VCS Simulation 202
- Chapter 13 205
- Assertions 205
- Appendix A 209
- Programs 209
- Appendix B 213
- VHDL Slave BFM Code Example 216
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