Altera Mentor Verification IP Altera Edition AMBA AXI4-St Bedienungsanleitung PDF herunterladen (Seite 217)

VHDL Master and Slave Test Programs

VHDL Slave BFM Code Example

Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3

217

April 2014

procedure ready_delay(signal tr_if : inout axi4stream_vhd_if_struct_t)

begin

-- Making TREADY '0'. This will consume one cycle.

execute_stream_ready(0, index, tr_if);

-- Two clock cycle wait. In total 3 clock wait.

for i in 0 to 1 loop

wait_on(AXI4STREAM_CLOCK_POSEDGE, index, tr_if);

end loop;

-- Making TREADY '1'.

execute_stream_ready(1, index, tr_if);

end ready_delay;

begin

--/////////////////////////////////////////////////////////////////////

-- Code user do not need to edit

--/////////////////////////////////////////////////////////////////////

process

variable trans: integer;

variable i : integer;

variable last : integer;

begin

--*******************

--** Initialisation **

--********************

wait_on(AXI4STREAM_RESET_POSEDGE, index, axi4stream_tr_if_0(index));

wait_on(AXI4STREAM_CLOCK_POSEDGE, index, axi4stream_tr_if_0(index));

------------------------/

-- Packet receiving:--

------------------------/

loop

create_slave_transaction(trans, index, axi4stream_tr_if_0(index));

i := 0;

last := 0;

while(last = 0) loop

if(m_insert_wait = '1') then

-- READY is through path

ready_delay(axi4stream_tr_if_0(index));

end if;

get_transfer(trans, i, last, index, axi4stream_tr_if_0(index));

i := i + 1;

end loop;

wait;

end process;

end slave_test_program_a;

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