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Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3
205
April 2014
Chapter 13
Assertions
The master, slave, and monitor BFMs all support error checking via the firing of one or more
assertions when a property detailed in the AMBA AXI4-Stream Protocol Specification has been
violated. Each assertion may be individually enabled/disabled using the set_config() function
for a particular BFM. The Property Reference column of Table 13-1 references the section
number in the AMBA AXI4-Stream Protocol Specification of the property the assertion covers.
Table 13-1. AXI4-Stream Assertions
Error Code Error Name Description Property
Ref
AXI4STREAM
-60000
AXI4STREAM_TDATA_CHANGED_
BEFORE_TREADY_
ON_INVALID_LANE
On an invalid byte lane (TSTRB =
0) the value of TDATA has
changed between TVALID asserted
and TREADY asserted.
2.2.1
AXI4STREAM
-60001
AXI4STREAM_TDATA_X_
ON_INVALID_LANE
On an invalid byte lane (TSTRB =
0), TDATA has an X value.
-
AXI4STREAM
-60002
AXI4STREAM_TDATA_Z_
ON_INVALID_LANE
On an invalid byte lane (TSTRB =
0), TDATA has a Z value.
-
AXI4STREAM
-60003
AXI4STREAM_TDATA_CHANGED_
BEFORE_TREADY_
ON_VALID_LANE
On a valid byte lane (TSTRB = 1)
the value of TDATA has changed
between TVALID asserted and
TREADY asserted.
2.2.1
AXI4STREAM
-60004
AXI4STREAM_TDATA_X_
ON_VALID_LANE
On a valid byte lane (TSTRB = 1),
TDATA has an X value.
-
AXI4STREAM
-60005
AXI4STREAM_TDATA_Z_
ON_VALID_LANE
On a valid byte lane (TSTRB = 1),
TDATA has a Z value.
-
AXI4STREAM
-60006
AXI4STREAM_TDEST_CHANGED_
BEFORE_TREADY
The value of TDEST has changed
between TVALID asserted and
TREADY asserted.
2.2.1
AXI4STREAM
-60007
AXI4STREAM_TDEST_X TDEST has an X value. -
AXI4STREAM
-60008
AXI4STREAM_TDEST_Z TDEST has a Z value. -
AXI4STREAM
-60009
AXI4STREAM_TID_CHANGED_
BEFORE_TREADY
The value of TID has changed
between TVALID asserted and
TREADY asserted.
2.2.1
AXI4STREAM
-60010
AXI4STREAM_TID_X TID has an X value. -
AXI4STREAM
-60011
AXI4STREAM_TID_Z TID has a Z value. -
- AMBA AXI4-Stream User Guide 1
- Table of Contents 3
- List of Examples 10
- List of Figures 11
- List of Tables 12
- About This User Guide 13
- Supported Simulators 13
- Simulator GCC Requirements 14
- Chapter 1 17
- Mentor VIP Altera Edition 17
- What Is a Transaction? 18
- AXI4-Stream Transactions 19
- Chapter 2 21
- SystemVerilog API Overview 21
- Configuration 22
- Creating Transactions 22
- Transaction Record 23
- Executing Transactions 26
- Waiting Events 27
- Access Transaction Record 27
- Operation Mode 28
- Handshake Delay 29
- Transfer Done 30
- Transaction Done 30
- Chapter 3 31
- SystemVerilog Master BFM 31
- Master BFM Configuration 32
- Master Assertions 34
- SystemVerilog Master API 35
- Returns 36
- Arguments config_name 37
- Chapter 4 43
- SystemVerilog Slave BFM 43
- SystemVerilog Slave API 47
- Chapter 5 55
- SystemVerilog Monitor BFM 55
- SystemVerilog Monitor API 59
- Chapter 6 67
- SystemVerilog Tutorials 67
- Chapter 7 75
- VHDL API Overview 75
- Test Program VHDL 76
- Chapter 8 87
- VHDL Master BFM API 91
- April 2014 100
- Prototype 118
- Arguments 118
- VHDL Master BFM 122
- VHDL Slave BFM 123
- Chapter 9 123
- Slave BFM Configuration 124
- Slave Assertions 125
- VHDL Slave BFM API 126
- Chapter 10 157
- VHDL Monitor BFM 157
- Monitor BFM Configuration 158
- Monitor Assertions 159
- VHDL Monitor BFM API 161
- Chapter 11 181
- VHDL Tutorials 181
- Master BFM Test Program 182
- Verifying a Master DUT 185
- Chapter 12 189
- Running the Qsys Tool 193
- Running a Simulation 195
- ModelSim Simulation 196
- Editing the modelsim.ini File 199
- Questa Simulation 200
- Cadence IES Simulation 200
- Synopsys VCS Simulation 202
- Chapter 13 205
- Assertions 205
- Appendix A 209
- Programs 209
- Appendix B 213
- VHDL Slave BFM Code Example 216
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