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In general, the HWLIB assumes to be part of the system software that is executing on the Hard Processor
System (HPS) in privileged supervisor mode and in the secure state.
The anticipated HWLIB clients include:
• Bare-Metal application developers
• Custom preloader and boot loader software developers
• Board support package developers
• Diagnostic tool developers
• Software driver developers
• Debug agent developers
• Board bring-up engineers
• Other developers requiring full access to SoC FPGA hardware capabilities
Feature Description
This section provides a description of the operational features and functional capabilities present in the
HWLIB. An overview and brief description of the HWLIB architecture is also presented.
The HWLIB is a software library architecturally comprised of two major functional components:
• SoC Abstraction Layer (SoCAL)
• Hardware Manager (HW Manager)
SoC Abstraction Layer (SoCAL)
The SoC Abstraction Layer (SoCAL) presents the software API closest to the actual HPS hardware. Its
purpose is to provide a logical interface abstraction and decoupling layer to the physical devices and
registers that comprise the hardware interface of the HPS.
The SoCAL provides the benefits of:
• A logical interface abstraction to the HPS physical devices and registers including the bit-fields
comprising them.
• A loosely coupled software interface to the underlying hardware that promotes software isolation from
hardware changes in the system address map and device register bit field layouts.
Hardware Manager (HW Manager)
The Hardware Manager (HW Manager) component provides a group of functional APIs that address
more complex configuration and operational control aspects of selected HPS resources.
The HW Manager functions have the following characteristics:
• Functions employ a combination of low level device operations provided by the SoCAL executed in a
specific sequence to effect a desired operation.
• Functions may employ cross functional (such as from different IP blocks) device operations to
implement a desired effect.
• Functions may have to satisfy specific timing constraints for the application of operations and
validation of expected device responses.
• Functions provide a level of user protection and error diagnostics through parameter constraint and
validation checks.
The HW Manager functions are implemented using elemental operations provided by the SoCAL API to
implement more complex functional capabilities and services. The HW Manager functions may also be
8-2
Feature Description
ug-1137
2014.12.15
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Hardware Library
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Overview 6
- Device Tree Binary 7
- Related Information 10
- Installation Folders 11
- Installing the SoC EDS 11
- Licensing 13
- Activating the License 14
- 5. Click Next 17
- Jumper Settings 21
- Start Eclipse 25
- Create New Project 25
- Set the Linker Script 28
- Write Application Source Code 31
- Build Application 34
- TestProject.axf executable 35
- Debug Application 36
- Create a New Project 45
- Figure 4-6: New Project 46
- Create a Linker Script 48
- Figure 4-14: Settings 55
- Figure 4-16: New Source File 57
- Figure 4-17: New Source File 58
- Figure 4-19: Build Project 60
- Starting the Eclipse IDE 71
- Application Console 76
- Sequence Sample Application 85
- Function 85
- Used Hardware 85
- Libraries APIs 85
- Description 85
- Debugging the Kernel 92
- Configuring Linux 97
- File Name Description 100
- Altera Corporation 101
- Getting Started Guides 101
- Send Feedback 101
- Figure 4-59: Browse Target 105
- 2014.12.15 108
- Getting Started with Tracing 111
- Figure 4-67: Trace Into ETF 112
- FPGA Triggering HPS Example 119
- HPS Triggering FPGA Example 123
- ARM DS-5 Altera Edition 126
- Bare-metal Project Management 127
- Creating Project 130
- Build Settings 134
- Build > Settings 135
- Creating a Project 136
- Figure 5-10: New Project 137
- Baremetal GCC. Click Finish 138
- Linker Script 140
- + Build > Settings 146
- Debugging 147
- Debug Configuration Options 150
- Connection Options 151
- Files Options 156
- Debugger Options 156
- RTOS Awareness 157
- Arguments 158
- Environment 158
- DTSL Options 159
- Cross Trigger Settings 160
- Trace Buffer Settings 161
- Cortex-A9 Settings 162
- STM Settings 163
- ETR Settings 163
- ETF Settings 164
- Embedded Command Shell 165
- HPS Preloader User Guide 166
- Hardware Handoff Files 168
- Using .tcl Scripts 169
- Option Required Description 171
- BSP Settings 174
- 2013.05.03 175
- Reset Assert Settings 179
- Preloader Compilation 180
- Preloader Image Tool 181
- Tool Usage 183
- Output Image Layout 184
- Hardware Library 188
- Feature Description 189
- Subscribe 191
- HPS Flash Programmer 192
- Option Short 193
- Required Description 193
- Supported Memory Devices 196
- Bare-Metal Compiler 198
- SD Card Boot Utility 199
- Tool Options 200
- Linux Compiler 202
- Device Tree Generator 205
- Yocto Plugin 206
- Support and Feedback 207
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