Altera SoC Embedded Design Suite Bedienungsanleitung Seite 161

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Figure 5-33: DTSL Configuration Editor - Cross Trigger
Trace Buffer Settings
The Trace Buffer tab allows the selection of the destination of the trace information. As mentioned in the
introduction, the destination can be one of the following:
None – meaning the tracing is disabled
ETR – using any memory buffer accessible by HPS
ETF – using the 32KB on-chip trace buffer
DSTREAM – using the 4GB buffer located in the DSTREAM
The DSTREAM option is available only if the Target connection is selected as DSTREAM in the Debug
Configuration.
Figure 5-34: DTSL Configuration Editor - Trace Buffer > Trace Capture Method
The Trace Buffer tab provides the option of selecting the timestamp frequency.
5-36
Trace Buffer Settings
ug-1137
2014.12.15
Altera Corporation
ARM DS-5 Altera Edition
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