Altera RLDRAM II Controller MegaCore Function Bedienungsanleitung Seite 8

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1–4 MegaCore Version 9.1 Altera Corporation
RLDRAM II Controller MegaCore Function User Guide November 2009
Performance and Resource Utilization
Optional fedback clock PLL—instantiated in non-DQS mode and
generates a capture clock for the datapath read capture and logic
path
OpenCore Plus Evaluation
With Altera’s free OpenCore Plus evaluation feature, you can perform
the following actions:
Simulate the behavior of a megafunction (Altera MegaCore function
or AMPP
SM
megafunction) within your system
Verify the functionality of your design, as well as evaluate its size
and speed quickly and easily
Generate time-limited device programming files for designs that
include MegaCore functions
Program a device and verify your design in hardware
You only need to obtain a license for the megafunction when you are
completely satisfied with its functionality and performance, and want to
take your design to production.
f For more information on OpenCore Plus hardware evaluation using the
RLDRAM II controller, refer to “OpenCore Plus Time-Out Behavior” on
page 2–12 and AN 320: OpenCore Plus Evaluation of Megafunctions.
Performance
and Resource
Utilization
Table 1–3 shows typical expected performance for the RLDRAM II
Controller MegaCore function, with the Quartus II software.
Table 1–3. Performance
Device Capture Mode
f
MAX
(MHz)
Stratix II
(EP2S60F1020C3)
Non-DQS 200
DQS 300
Stratix II GX
(EP2SGX30CF780C3)
Non-DQS 200
DQS 300
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