Altera RLDRAM II Controller MegaCore Function Bedienungsanleitung PDF herunterladen (Seite 25)

Altera Corporation MegaCore Version 9.1 2–15

November 2009 RLDRAM II Controller MegaCore Function User Guide

Functional Description

Figure 2–10. Testbench & Example Design

Table 2–2 describes the files that are associated with the example design

and the testbench.

The testbench instantiates an RLDRAM II model and generates a

reference clock for the PLL.

1 Altera does not provide a memory simulation model. You must

download one or use your own.

Example Driver

PLLclock_source

test_complete

pnf_persist

Example Design

Testbench

RLDRAM II Controller

RLDRAM II

Model

DLL

pnf_per_byte

Table 2–2. Example Design & Testbench Files

Filename Description

<top-level name>_tb.v or .vhd (1) Testbench for the example design.

<top-level name>.vhd or .v (1) Example design.

rldramii_pll_<device name>.vhd or .v Example PLL, which you should

configure to match your frequency.

rldramii_fbpll_<device name>.vhd or

Fedback PLL

<variation name>_example_driver.v

or .vhd (2)

Example driver.

<variation name> .v or .vhd (2) RLDRAM II controller.

Notes to Ta b le 2 –2 :

(1) <top-level name> is the name of the Quartus II project top-level entity.

(2) <variation name> is the variation name.

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