Altera RLDRAM II Controller MegaCore Function Bedienungsanleitung PDF herunterladen (Seite 32)

2–22 MegaCore Version 9.1 Altera Corporation

RLDRAM II Controller MegaCore Function User Guide November 2009

Signals

Figure 2–16. Single Refresh Command

Signals

Table 2–3 shows the system signals.

clk

Local Interface

local_write_req

local_read_req

local_refresh_req

local_addr[]

local_bank_addr[]

local_wdata_req

local_wdata[]

local_dm[]

RLDRAM II Interface

rldramii_clk

rldramii_clk_n

rldramii_cs_n

rldramii_we_n

rldramii_ref_n

rldramii_a[]

rldramii_ba[]

rldramii_dm[]

rldramii_dq[]

rldramii_qk[]

rldramii_qvld[]

A A BB

01 23 45 67 01 2323

A BA

0 1 2 3 4 5 6 77

11 1100

Table 2–3. System Signals (Part 1 of 3)

Name

Width

(Bits)

Direction Description

clk

1 Input System clock for the control logic and

datapath.

write_clk

1 Input Shifted clock that center aligns write data

to the memory.

1 2 ... 27 28 29 30 31 32 33 34 35 36 37 ... 61 62

RLDRAM II Controller 1
MegaCore Function User Guide 1
UG-RLDRAM-8.1 2
Contents 3
Additional Information 4
1. About This MegaCore 5
Function 5
Features 6
General 6
Description 6
(1) Non-DQS mode only 7
Performance 8
Utilization 8
2. Functional Description 11
Control Logic 12
Datapath 13
<signal>_1 are present 14
Memory Clock Generator 15
Pipeline Registers 16
DQS Group 16
Functional Description 17
Notes to Figure 2–4: 17
Datapath Example 18
Figure 2–6. Example Datapath 19
Device-Level 22
Configuration 22
Example Design 24
Interfaces 26
Refreshes 31
system signals 32
Direction Description 33
Parameters 38
Parameter Range Description 40
Project Settings 42
MegaCore 43
Verification 43
MegaCore Verification 44
3. Getting Started 45
RLDRAM II 46
Controller 46
Walkthrough 46
Launch IP Toolbench 48
Step 1: Parameterize 49
Step 2: Constraints 51
Step 3: Set Up Simulation 52
Step 4: Generate 52
Simulate the 55
Simulate the Example Design 56
Edit the PLL 57
Compile the 58
Program a 59
Implement Your 59
Set Up Licensing 59
Typographic 62
Conventions 62

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