Altera QDRII SRAM Controller MegaCore Function Bedienungsanleitung PDF herunterladen (Seite 61)

Altera Corporation MegaCore Version 9.1 3–29

November 2009 QDRII SRAM Controller MegaCore Function User Guide

Functional Description

The testbench instantiates a QDRII SRAM model, a reference clock for the

PLL, and model for the system board memory trace delays.

Altera provides a Verilog HDL simulation model. The model is a

behavioral model to verify the design but does not simulate any delays.

Altera recommends that you replace the model with the specific model

from your memory vendor.

f For more details on how to run the simulation script, refer to “Simulate

the Example Design” on page 2–11.

Constraints

IP Toolbench generates a constraints script,

add_constraints_for_<variation name>.tcl, which is a set of Quartus II

assignments that are required to successfully compile the example

design.

1 When the constraints script runs, it creates another script,

remove_constraints_for_<variation name>.tcl, which you can

use to remove the constraints from your design.

The constraints script implements the following types of assignments:

■ cqn, cq, and q capture pins placement

■ Capacitance loading

■ cq pin set to non-global signal

■ I/O type for all interface pins

■ Cut timing assignments for false timing paths

Parameters

The parameters can only be set in IP Toolbench (refer to “Step 1:

Parameterize” on page 2–5).

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Altera QDRII SRAM Controller MegaCore Function Bedienungsanleitung Seite 61