Altera QDRII SRAM Controller MegaCore Function Bedienungsanleitung PDF herunterladen (Seite 39)

Altera Corporation MegaCore Version 9.1 3–7

November 2009 QDRII SRAM Controller MegaCore Function User Guide

Functional Description

Clock Generator

The clock generator generates the memory signals k and kn. The clocks

are derived from the PLL-generated clock and are shifted by 90 to the

system clock.

Address & Command Output Registers

The address and command output registers generate the following

outputs:

■ Address

■ Read

■ Write

■ Write byte enable

There is one set of signals per device on a board.

With more than one device on a board, a suffix indicates the width

position and depth position. The width can be anything up to what the

device supports (for example, you can make a 72-bit interface out of four

18-bit interfaces). The depth is limited to 2.

For a device depth of two, you must connect the reads and writes to each

device. The top address bit going into the address command top-level file

is a device select, which selects device 0 or 1 by setting the read and write

of the unused device to 1.

Write Registers

The write registers comprise write I/O blocks going to the memory. For

each memory in width, the controller creates a data bus. For a device

depth of two, the controller shares the data bus between the two devices.

The Capture Group Module

The capture group module comprises the following elements:

■ CQ/CQN group module

■ Read capture registers

The controller uses the 90shifted cq and cqn clocks for the capture

registers of the q bus.

When captured, the controller synchronizes the two words on a double

width bus.

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Altera QDRII SRAM Controller MegaCore Function Bedienungsanleitung Seite 39