Altera QDRII SRAM Controller MegaCore Function Bedienungsanleitung PDF herunterladen (Seite 6)

1–2 MegaCore Version 9.1 Altera Corporation

QDRII SRAM Controller MegaCore Function User Guide November 2009

Features

Table 1–2 shows the level of support offered by the QDRII SRAM

Controller MegaCore function to each Altera device family.

Features

■ Support for burst of two and four memory type

■ Support for 8-, 18-, and 36-bit QDRII interfaces

■ Support for two-times and four-times data width on the local side

(four-times for burst of four only)

■ Operates at 300 MHz for QDRII and QDRII+ SRAM

■ Automatic concatenation of consecutive reads and writes (narrow

local bus width mode only)

■ Easy-to-use IP Toolbench interface

■ IP functional simulation models for use in Altera-supported VHDL

and Verilog HDL simulators

■ Support for OpenCore Plus evaluation

General

Description

The QDRII SRAM Controller MegaCore function provides an easy-to-use

interface to QDRII SRAM modules. The QDRII SRAM Controller ensures

that the placement and timing are in line with QDRII specifications.

The QDRII SRAM Controller is optimized for Altera Stratix series. The

advanced features available in these devices allow you to interface

directly to QDRII SRAM devices.

Figure 1–1 shows a system-level diagram including the example design

that the QDRII SRAM Controller MegaCore function creates for you.

Table 1–2. Device Family Support

Device Family Support

HardCopy

Preliminary

Stratix

Full

Stratix

II Full

Stratix

II GX

Full

Stratix GX Full

Other device families (1) No support

Note to Ta b le 1 –2 :

(1) For more information on support for Stratix III or Stratix IV devices, contact

Altera.

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