Altera QDRII SRAM Controller MegaCore Function Bedienungsanleitung PDF herunterladen (Seite 33)

Altera Corporation MegaCore Version 9.1 3–1

November 2009

3. Functional Description

Block

Description

Figure 3–1 shows a block diagram of the QDR SRAM controller

MegaCore function.

Figure 3–1. QDRII SRAM Controller Block Diagram (1)

Notes to Figure 3–1:

(1) You can edit the qdrii_ prefix.

The QDRII SRAM Controller comprises the following three parts:

■ The control logic gets read and write requests from the Avalon

interface and turn them into QDRII SRAM read and write requests,

with the correct timing and concatenating consecutive addresses

where applicable.

■ The resynchronization and pipeline logic provides the

resynchronization system, the training block, and the optional

pipeline logic.

■ The datapath contains all the I/O and the clock generation.

avl_clk

avl_clk_wr

avl_resetn

dll_delay_ctrl

resynch_clk

avl_addr_wr

avl_byteen_wr

avl_chipselect_wr

avl_data_wr

avl_write

avl_wait_request_wr

avl_addr_rd

avl_byteen_rd

avl_chipselect_rd

avl_read

avl_data_rd

avl_datavalid_rd

avl_wait_request_rd

Control

Logic

(Encrypted)

QDRII SRAM Controller

Datapath

(Clear Text)

Resynchronization

& Pipeline Logic

(Clear Text)

qdrii_a

qdrii_bwsn

qdrii_cq

qdrii_cqn

qdrii_d

qdrii_k

qdrii_kn

qdrii_q

qdrii_rpsn

qdrii_wpns

1 2 ... 28 29 30 31 32 33 34 35 36 37 38 ... 67 68

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