Altera POS-PHY Level 4 IP Core Bedienungsanleitung Seite 85
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Chapter 5: Functional Description—Transmitter 5–15
Error Flagging and Handling
December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
If a SOP is detected during an open packet, then
err_aN_meopN
is asserted. The packet
is terminated with an EOP-Abort, and data is ignored for that port until an EOP is
received.
If a MTY is non-zero when a missing EOP is not asserted, then
err_aN_meopN
is
asserted. The packet is terminated with an EOP-Abort, and data is ignored for that
port until a SOP is received.
The Atlantic FIFO buffer error checker block also handles overflows. If an overflow
occurs, the error checker block rejects all inputs until the buffer is drained of all of its
data (
err_aN_fifo_oflwN
is asserted), however existing internal calendar values are
left untouched. Any open packets are truncated with the EOP and ERR signals (this
leads to EOP abort on the SPI-4.2 bus). If the last successful write immediately before
the overflow was an EOP, then truncation is unnecessary. All writes to the buffer are
discarded and ignored. The Atlantic write
aN_atxdav
signal is forced low (to indicate
to the user logic to stop writing) during the flushing operation. The buffer is fully
flushed out (due to the assurance that no EOP is present in the buffer). Flushing is
accomplished by the transmitter IP core as it continues to read data from the buffer.
Complete packets already written to the buffer before the overflow occurred are not
corrupted and are safely transmitted. Once the buffer is empty, the
aN_atxdav
signal is
released and the
err_aN_fifo_oflwN
flag is deasserted low. Writes to the buffer are
ignored until a SOP is received, for each port that had an open packet during the
overflow. Refer to Figure 5–11 on page 5–16.
Missing SOP
Figure 5–7 and Figure 5–8 show missing SOP.
Figure 5–7. Atlantic Interface with Missing SOP
Figure 5–8. Output from Atlantic Error Checker Block (Corrected MSOP)
Missing SOP
aN_atx
eop
aN_atx
err
aN_atxtclk
aN_atxena
aN_atxsop
err_ry_msopN
aN_atx
eop
aN_atx
err
aN_atxtclk
aN_atxena
aN_atxsop
- User Guide 1
- POS-PHY Level 4 IP Core 1
- 1. About This IP Core 3
- General Description 5
- Interfaces & Protocols 6
- IP Core Verification 7
- OpenCore Plus IP Evaluation 9
- 2. Getting Started 11
- Using the Parameter Editor 12
- Upgrading Outdated IP Cores 13
- Specify Parameters 15
- Simulate the Design 17
- 3. Parameter Settings 21
- LVDS Data Rate 22
- PLL Input Frequency 23
- Data Path Width 23
- Buffer Mode 23
- Basic Parameters 24
- Atlantic FIFO Buffer Clock 25
- Atlantic Interface Width 25
- Optional Features 26
- Transmitter Options 27
- Receiver Options 28
- Starving Starving Starving 29
- Starving Hungry Hungry 29
- Starving Satisfied Satisfied 29
- FIFO RAM Blocks 30
- Note to Table 3–5: 31
- Protocol Parameters 32
- Features 39
- Block Description 39
- ALTLVDS_RX IP Core 41
- Data Processor (rx_data_proc) 42
- Atlantic Buffers 43
- Individual Buffers 44
- Status Processor 45
- Notes to Figure 4–3: 46
- Note to Table 4–1: 47
- Notes to Figure 4–4: 48
- Requirements for rxsys_clk 49
- Reset Structure 50
- Error Flagging and Handling 50
- SPI-4.2 Protocol Errors 51
- Notes to Table 4–3: 53
- DIP-4 Marking 54
- Notes to Figure 4–8: 56
- Missing SOP 59
- Missing EOP 60
- Note to Table 4–7: 62
- Note to Table 4–8: 63
- Note to Table 4–9: 63
- Latency Information 68
- Data Processor (tx_data_proc) 74
- Status Bypass Port 77
- Clock Structure 78
- Multiple Clock Domain 79
- Notes to Figure 5–4: 80
- Note to Table 5–5: 88
- 6. Testbench 99
- Variation 100
- Receiver 100
- Receiver Testbench Examples 101
- 6–4 Chapter 6: Testbench 102
- Chapter 6: Testbench 6–5 103
- 6–6 Chapter 6: Testbench 104
- Chapter 6: Testbench 6–7 105
- 6–8 Chapter 6: Testbench 106
- A. Start-Up Sequence 107
- Troubleshooting 109
- Issues and Tips—Miscellaneous 111
- Separate PLLs 113
- Shared PLL 113
- "<rx_pll>" 114
- Note to Table C–1: 115
- D. Board Design 117
- Probe Points 118
- Spare Pins 119
- JTAG Scan Chain 119
- D–4 Appendix D: Board Design 120
- Design for Testability 120
- Introduction 121
- Static Alignment 125
- Dynamic Alignment 126
- Altera Solutions 126
- Dynamic Phase Alignment (DPA) 127
- AC Timing Analysis 128
- Budgets 129
- G. Conversion from v2.2.x 131
- Receiver Signals 132
- Transmitter Signals 134
- Additional Information 139
- Note to Table: 140
- Additional Information Info–3 141
- Typographic Conventions 141
- Info–4 Additional Information 142
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