Altera POS-PHY Level 4 IP Core Bedienungsanleitung Seite 133
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Appendix G: Conversion from v2.2.x G–3
Receiver Signals
December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
err_ry_msopN err_xx_msop
In version 2.2.x, these signals are in the
rrefclk
domain; in version 2.3.0, these
signals are in the
rxsys_clk
domain.
err_ry_meopN err_xx_meop
stat_ry_mp_erradr stat_xx_mp_erradr
ctl_ry_ae ctl_xx_rxae
ctl_ry_af ctl_xx_rxaf
ctl_ry_fifostatoverride ctl_rr_fifostatoverride
ctl_ry_extstat_val ctl_a0_extstat_val
No change.
ctl_ry_extstat_adr ctl_a0_extstat_adr
ctl_ry_extstat ctl_a0_extstat
ctl_rs_statedge ctl_rr_statedge
ctl_ry_rsfrm ctl_rr_rsfrm
In version 2.2.x, these signals are in the
rrefclk
domain; in version 2.3.0, these
signals are in the
rxsys_clk
domain.
stat_ry_disabled –
New.
stat_ry_dip2state stat_rr_dip2state
In version 2.2.x, these signals are in the
rrefclk
domain; in version 2.3.0, these
signals are in the
rxsys_clk
domain.
ctl_ry_callen ctl_rr_rxcallen
New restrictions. The system does not function
properly if these signals are set incorrectly.
Refer to Table C–1 on page C–1 for further
details.
ctl_ry_calm ctl_rr_rxcalm
stat_ry_calsel –
New.
rav_clk
–
New Avalon-MM interface signals. These
signals are present only when Asymmetric Port
Support is turned on.
rav_reset_n
tied high in
the IP Toolbench top-level file.
rav_reset_n
–
rav_address
–
rav_chipselect
–
rav_write
–
rav_read
–
rav_writedata
–
rav_readdata
–
rav_waitrequest
–
err_rd_dpa err_rr_dpa
No change.
stat_rd_dpa_locked stat_rr_dpa_locked
stat_rd_dpa_lvds_locked stat_rr_dpa_lvds_locked
ctl_rd_dpa_force_unlock ctl_rr_dpa_force_unlock
stat_rd_rdat_sync stat_rr_rdat_sync
No change.
stat_rd_tp_flag stat_rr_tp_flag
stat_rd_rsv_cw stat_rr_rsv_cw
ctl_rd_dip4_bad_threshold ctl_rr_dip4_bad_threshold
Reduced to 4-bit only.
ctl_rd_dip4_good_threshold ctl_rr_dip4_good_threshold
Table G–1. Receiver Signal Changes (Part 2 of 3)
Version 2.4.x and 2.3.x Signal
Name
Version 2.2.x Signal Name Notes
- User Guide 1
- POS-PHY Level 4 IP Core 1
- 1. About This IP Core 3
- General Description 5
- Interfaces & Protocols 6
- IP Core Verification 7
- OpenCore Plus IP Evaluation 9
- 2. Getting Started 11
- Using the Parameter Editor 12
- Upgrading Outdated IP Cores 13
- Specify Parameters 15
- Simulate the Design 17
- 3. Parameter Settings 21
- LVDS Data Rate 22
- PLL Input Frequency 23
- Data Path Width 23
- Buffer Mode 23
- Basic Parameters 24
- Atlantic FIFO Buffer Clock 25
- Atlantic Interface Width 25
- Optional Features 26
- Transmitter Options 27
- Receiver Options 28
- Starving Starving Starving 29
- Starving Hungry Hungry 29
- Starving Satisfied Satisfied 29
- FIFO RAM Blocks 30
- Note to Table 3–5: 31
- Protocol Parameters 32
- Features 39
- Block Description 39
- ALTLVDS_RX IP Core 41
- Data Processor (rx_data_proc) 42
- Atlantic Buffers 43
- Individual Buffers 44
- Status Processor 45
- Notes to Figure 4–3: 46
- Note to Table 4–1: 47
- Notes to Figure 4–4: 48
- Requirements for rxsys_clk 49
- Reset Structure 50
- Error Flagging and Handling 50
- SPI-4.2 Protocol Errors 51
- Notes to Table 4–3: 53
- DIP-4 Marking 54
- Notes to Figure 4–8: 56
- Missing SOP 59
- Missing EOP 60
- Note to Table 4–7: 62
- Note to Table 4–8: 63
- Note to Table 4–9: 63
- Latency Information 68
- Data Processor (tx_data_proc) 74
- Status Bypass Port 77
- Clock Structure 78
- Multiple Clock Domain 79
- Notes to Figure 5–4: 80
- Note to Table 5–5: 88
- 6. Testbench 99
- Variation 100
- Receiver 100
- Receiver Testbench Examples 101
- 6–4 Chapter 6: Testbench 102
- Chapter 6: Testbench 6–5 103
- 6–6 Chapter 6: Testbench 104
- Chapter 6: Testbench 6–7 105
- 6–8 Chapter 6: Testbench 106
- A. Start-Up Sequence 107
- Troubleshooting 109
- Issues and Tips—Miscellaneous 111
- Separate PLLs 113
- Shared PLL 113
- "<rx_pll>" 114
- Note to Table C–1: 115
- D. Board Design 117
- Probe Points 118
- Spare Pins 119
- JTAG Scan Chain 119
- D–4 Appendix D: Board Design 120
- Design for Testability 120
- Introduction 121
- Static Alignment 125
- Dynamic Alignment 126
- Altera Solutions 126
- Dynamic Phase Alignment (DPA) 127
- AC Timing Analysis 128
- Budgets 129
- G. Conversion from v2.2.x 131
- Receiver Signals 132
- Transmitter Signals 134
- Additional Information 139
- Note to Table: 140
- Additional Information Info–3 141
- Typographic Conventions 141
- Info–4 Additional Information 142
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