Altera POS-PHY Level 4 IP Core Bedienungsanleitung PDF herunterladen (Seite 128)

F–4 Appendix F: Static and Dynamic Phase Alignment

AC Timing Analysis

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

f For more information on the use of DPA in the POS-PHY Level 4 IP core, refer to

“DPA Channel Aligner (rx_data_phy_dpa)” on page 4–2.

f For more information on using dynamic phase alignment, refer to the following

documents:

■ High-Speed Differential I/O Interfaces with DPA in Stratix II Devices chapter of the

Stratix II Device Handbook

■ AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices

■ The Need for Dynamic Phase Alignment in High-Speed FPGAs White Paper

AC Timing Analysis

Specifications for this interface allow two sets of timing relationships between the

sender and receiver: static and dynamic mode. In the static alignment mode, all data

obeys a common set of timing parameters (for example, set up and hold times with

respect to a sampling clock). In the dynamic alignment mode, a per-bit timing

relationship applies.

This section describes the timing analysis for various configurations and components.

These timing components are referenced to Figure F–3 on page F–5, which shows the

timing path as related to the paths followed by the clock and data signals through the

user’s system. Figure F–4 on page F–5 references the timing values to the clock and

data edges.

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Altera POS-PHY Level 4 IP Core Bedienungsanleitung Seite 128