Altera FIR Compiler Bedienungsanleitung PDF herunterladen (Seite 65)

Chapter 4: Functional Description 4–23

Timing Diagrams

For information about how to pre-calculate coefficients, refer to “Coefficient

Reloading and Reordering” on page 4–4.

In serial and multibit serial filters, coef_we is effective two clock cycles ahead of the

first coef_in data and lasts until the last coef_in data is transmitted. In parallel

filters, coef_we only needs to be effective one clock cycle ahead of the first coef_in

data. To reload another set of coefficients, coef_we must be low for at least one clock

cycle. The reload clock does not have to be the same clock as the one used by the FIR

calculation.

Figure 4–24 shows the serial and multibit serial coefficient reloading timing diagram.

Figure 4–25 shows the parallel coefficient reloading timing diagram.

1 Serial, multibit serial, and parallel FIR architectures use a distributed arithmetic

algorithm. In the algorithm, look-up tables store partial products of the coefficient; the

first data of the partial product is always 0. When reloading pre-calculated coefficients

in serial, multibit serial, and parallel architectures, the first reloading coefficient is

always 0.

For information about how to pre-calculate coefficients, refer to “Coefficient

Reloading and Reordering” on page 4–4.

Figure 4–24. Serial and Multibit Serial Coefficient Reloading Timing Diagram

clk

reset_n

ast_sink_ready

ast_sink_data

coef_in_clk

coef_we

coef_in

coef_set

coef_set_in

ast_source_valid

ast_source_data

0 1 -1 0-1

0 0 7 5 12 0

coef_we should be two clock cycles ahead of coef_in (First data is always 0)

Clock to reload coefficients Precalculated coefficient values

Figure 4–25. Parallel Coefficient Reloading Timing Diagram

clk

reset_n

ast_sink_data

coef_in_clk

coef_we

coef_in

coef_set

coef_set_in

0 0 7 5 12 0 7

coef_we should be one clock cycle ahead of coef_in (First data is always 0)

1 2 ... 60 61 62 63 64 65 66 67 68 69 70 ... 75 76

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