Altera FIR Compiler Bedienungsanleitung PDF herunterladen (Seite 58)

4–16 Chapter 4: Functional Description

Signals

FIR Compiler User Guide © May 2011 Altera Corporation

The data transfer in Figure 4–13 occurs on cycles 1, 2, 4, and five, when both ready

and valid are asserted. During cycle 1, startofpacket is asserted, and the first

data is transferred. During cycle 5, endofpacket is asserted indicating that this is the

end of the packet.

The channel signal indicates the channel index associated with the data. For

example, on cycle 1, the data D

associated with channel 0 is available.

The error signal stays at value 00 during a normal operation. Whenever a value

other than 00 is received from the data source (as in Figure 4–11), or a packet error is

detected by the Avalon-ST controller of the FIR filter, the controller is reset and waits

for the next valid startofpacket signal. It also transmits the received error signal

from its data source module error output.

1 The error signal only resets the Avalon-ST controller and not the design. Therefore,

the output data produced after an error condition may contain invalid data for several

cycles. It is recommended that a global reset is applied whenever an error message is

present in the system.

Signals

Table 4–3 lists the input and output signals for the FIR Compiler MegaCore function.

Table 4–3. FIR Compiler Signals (Part 1 of 2)

Signal Direction Description

clk Input Clock signal used to clock all internal FIR filter registers.

enable Input Active high clock enable signal. This pin appears when the Add global clock

enable pin option is selected on the Parameterize FIR Compiler page. (The

Avalon-ST registers are NOT connected to this clock enable.)

reset_n Input Synchronous active low reset signal. Resets the FIR filter control circuit on the

rising edge of clk. This signal should last longer than one clock cycle.

ast_sink_ready Output Asserted by the FIR filter when it is able to accept data in the current clock cycle.

ast_sink_valid Input Asserted when input data is valid. When ast_sink_valid is not asserted, the

FIR processing is stopped if new data is required and no data is left in the Avalon-

ST input FIFO. Otherwise, the FIR processing continues.

ast_sink_data Input Sample input data.

ast_sink_sop Input Marks the start of the incoming sample group. The start of packet (SOP) is

interpreted as a sample from channel 0.

ast_sink_eop Input Marks the end of the incoming sample group. If there is data associated with N

channels, the end of packet (EOP) must be high when the sample belonging to the

last channel (that is, channel N-1), is presented at the data input.

ast_sink_error Input Error signal indicating Avalon-ST protocol violations on the sink side:

■ 00: No error

■ 01: Missing SOP

■ 10: Missing EOP

■ 11: Unexpected EOP

Other types of errors are also marked as 11.

ast_source_ready Input Asserted by the downstream module if it is able to accept data.

ast_source_valid Output Asserted by the FIR filter when there is valid data to output.

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