Altera Stratix IV GX FPGA Development Board Bedienungsanleitung PDF herunterladen (Seite 64)

2–56 Chapter 2: Board Components

Memory

Stratix IV GX FPGA Development Board August 2012 Altera Corporation

Reference Manual

Table 2–52 lists the QDRII+ top port 1 pin assignments, signal names, and functions.

The signal names and types are relative to the Stratix IV GX device in terms of I/O

setting and direction.

Table 2–52. QDRII+ Top Port 1 Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)

Board Reference Description

Schematic Signal Name

I/O Standard

Stratix IV GX

Device

Pin Number

U7.A10 Address bus

QDR2TOP1_A19

1.5-V HSTL Class I F20

U7.A3 Address bus

QDR2TOP1_A18

1.5-V HSTL Class I B17

U7.A9 Address bus

QDR2TOP1_A17

1.5-V HSTL Class I G20

U7.R7 Address bus

QDR2TOP1_A16

1.5-V HSTL Class I E17

U7.R5 Address bus

QDR2TOP1_A15

1.5-V HSTL Class I J18

U7.R4 Address bus

QDR2TOP1_A14

1.5-V HSTL Class I M19

U7.R3 Address bus

QDR2TOP1_A13

1.5-V HSTL Class I R18

U7.P8 Address bus

QDR2TOP1_A12

1.5-V HSTL Class I F18

U7.P7 Address bus

QDR2TOP1_A11

1.5-V HSTL Class I F17

U7.P5 Address bus

QDR2TOP1_A10

1.5-V HSTL Class I F16

U7.P4 Address bus

QDR2TOP1_A9

1.5-V HSTL Class I P18

U7.N7 Address bus

QDR2TOP1_A8

1.5-V HSTL Class I D17

U7.N6 Address bus

QDR2TOP1_A7

1.5-V HSTL Class I G18

U7.N5 Address bus

QDR2TOP1_A6

1.5-V HSTL Class I L19

U7.C7 Address bus

QDR2TOP1_A5

1.5-V HSTL Class I G19

U7.C5 Address bus

QDR2TOP1_A4

1.5-V HSTL Class I C18

U7.B8 Address bus

QDR2TOP1_A3

1.5-V HSTL Class I A18

U7.B4 Address bus

QDR2TOP1_A2

1.5-V HSTL Class I A17

U7.R8 Address bus

QDR2TOP1_A1

1.5-V HSTL Class I H19

U7.R9 Address bus

QDR2TOP1_A0

1.5-V HSTL Class I C17

U7.N2 Write data bus

QDR2TOP1_D17

1.5-V HSTL Class I G15

U7.M3 Write data bus

QDR2TOP1_D16

1.5-V HSTL Class I F15

U7.L3 Write data bus

QDR2TOP1_D15

1.5-V HSTL Class I E16

U7.J3 Write data bus

QDR2TOP1_D14

1.5-V HSTL Class I D16

U7.G2 Write data bus

QDR2TOP1_D13

1.5-V HSTL Class I C15

U7.F3 Write data bus

QDR2TOP1_D12

1.5-V HSTL Class I C16

U7.D2 Write data bus

QDR2TOP1_D11

1.5-V HSTL Class I B16

U7.C3 Write data bus

QDR2TOP1_D10

1.5-V HSTL Class I A16

U7.B3 Write data bus

QDR2TOP1_D9

1.5-V HSTL Class I G16

U7.C11 Write data bus

QDR2TOP1_D8

1.5-V HSTL Class I G17

U7.D11 Write data bus

QDR2TOP1_D7

1.5-V HSTL Class I J16

U7.E10 Write data bus

QDR2TOP1_D6

1.5-V HSTL Class I K16

U7.G11 Write data bus

QDR2TOP1_D5

1.5-V HSTL Class I L16

U7.J11 Write data bus

QDR2TOP1_D4

1.5-V HSTL Class I P17

U7.K10 Write data bus

QDR2TOP1_D3

1.5-V HSTL Class I K17

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