Altera Stratix IV GX FPGA Development Board Bedienungsanleitung PDF herunterladen (Seite 14)

2–6 Chapter 2: Board Components

Featured Device: Stratix IV GX Device

Stratix IV GX FPGA Development Board August 2012 Altera Corporation

Reference Manual

I/O Resources

Figure 2–2 shows the bank organization and I/O count for the EP4SGX230 device in

the 1517-pin FineLine BGA package.

Table 2–4 lists the Stratix IV GX device pin count and usage by function on the

development board.

Figure 2–2. EP4SGX230KF40 Device I/O Bank Diagram

Bank 8A 40

Bank 8B 24

Bank 8C 32

Bank 7C 32

Bank 6A 48

Bank 6C

EP4SGX230

EP4SGX290

EP4SGX360

EP4SGX530

Bank

Name

Number

of I/Os

Bank 5C 40

Bank 5A

Bank 1A

Bank 1C

Bank 2C

Bank 2A 48

Bank 7B 24

Bank 7A 40

Bank

Name

Number

of I/Os

Bank 3A40

Bank 3B24

Bank 3C32

Bank 4C32

Bank 4B24

Bank 4A40

Bank

GXBL2

Bank

GXBL1

Bank

GXBL0

Bank

GXBR2

Bank

GXBR1

Bank

GXBR0

*Number of

Transceiver

Channel

Table 2–4. Stratix IV GX Device Pin Count and Usage (Part 1 of 2)

Function I/O Standard I/O Count Special Pins

DDR3 ×16 Top Port 1.5-V SSTL 49 2 Diff ×8 DQS

DDR3 ×64 Bottom Port 1.5-V SSTL 117 8 Diff ×8 DQS

QDRII+ Top Port 0 1.5-V HSTL 66 1 Diff ×18 DQS

QDRII+ Top Port 1 1.5-V HSTL 66 1 Diff ×18 DQS

Flash, SRAM, MAX FSM Bus 2.5-V CMOS 78 —

PCI Express ×8 2.5-V CMOS + XCVR 38 1 REFCLK, 8 XCVR

HSMC Port A 2.5-V CMOS + LVDS + XCVR 116 8 XCVR, 17 LVDS, 5 Clock Inputs

HSMC Port B 2.5-V CMOS + LVDS + XCVR 116 6 XCVR, 17 LVDS, 5 Clock Inputs

Gigabit Ethernet 2.5-V CMOS + LVDS 8 1 LVDS

HDMI Video 2.5-V CMOS 39 —

SDI Video XCVR 7 1 XCVR

Buttons 2.5-V CMOS 4 1 DEV_CLRn

Switches 2.5-V CMOS 8 —

LCD 2.5-V CMOS 11 —

LEDs 2.5-V CMOS 24 —

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 81 82

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