Altera Stratix IV GX FPGA Development Board Bedienungsanleitung PDF herunterladen (Seite 33)

Chapter 2: Board Components 2–25

Clock Circuitry

August 2012 Altera Corporation Stratix IV GX FPGA Development Board

Reference Manual

Stratix IV GX FPGA Clock Outputs

Figure 2–8 shows the Stratix IV GX FPGA development board clock outputs.

Table 2–21 lists the clock outputs for the Stratix IV GX FPGA development board.

Figure 2–8. Stratix IV GX FPGA Development Board Clock Outputs

B1B2

B6B5

SRAM_CLK

MAX2_CLK

2.5V, 50

OCT

2.5V, 50

OCT

SMA

PLL

HSMA_CLK_OUT_P2

LVDS, NO OCT

FLASH_CLK

2.5V, 50

OCT

CLKOUT_SMA

2.5V, 50

OCT

HDMI_CLK

1.8V, 50 Ω OCT

HSMA_CLK_OUT_P1

LVDS, NO OCT

HSMB_CLK_OUT_P1

LVDS, NO OCT

HSMB_CLK_OUT_P2

LVDS, NO OCT

DDR3BOT_CK_P

SSTL-15 Class I

DDR3BOT_CK_N

SSTL-15 Class I

DDR3TOP_CK_P

SSTL-15 Class I, 50 Ω OCT

DDR3TOP_CK_N

SSTL-15 Class I, 50 Ω OCT

QDR2_TOP0_K_P

1.5V HSTL Class I, 50 Ω OCT

QDR2_TOP0_K_N

1.5V HSTL Class I, 50 Ω OCT

QDR2_TOP1_K_P

1.5V HSTL Class I, 50 Ω OCT

QDR2_TOP1_K_N

1.5V HSTL Class I, 50 Ω OCT

Table 2–21. Stratix IV GX FPGA Development Board Clock Outputs (Part 1 of 2)

Connector Schematic Signal Name Pin I/O Standard Description

SMA

CLKOUT_SMA

W33 2.5-V FPGA CMOS output or general purpose I/O (GPIO)

Samtec HSMC

HSMA_CLK_OUT0

AM29 2.5-V FPGA CMOS output or GPIO

Samtec HSMC

HSMA_CLK_OUT_P1

AL10

LVDS or 2.5-V LVDS output or two 2.5-V CMOS outputs.

HSMA_CLK_OUT_N1

AM10

Samtec HSMC

HSMA_CLK_OUT_P2

AF13

LVDS or 2.5-V LVDS output or two 2.5-V CMOS outputs.

HSMA_CLK_OUT_N2

AG13

Samtec HSMC

HSMB_CLK_OUT0

AK29 2.5-V FPGA CMOS output or GPIO

Samtec HSMC

HSMB_CLK_OUT_P1

LVDS or 2.5-V LVDS output or two 2.5-V CMOS outputs.

HSMB_CLK_OUT_N1

1 2 ... 28 29 30 31 32 33 34 35 36 37 38 ... 81 82

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