Altera Mentor Verification IP Altera Edition AMBA AXI3/4T Bedienungsanleitung PDF herunterladen (Seite 177)

100

101

SystemVerilog Tutorials

Verifying a Master DUT

Mentor VIP AE AXI3/4 User Guide, V10.2b

159

September 2013

You can edit this function to change the WREADY signal delay.

Example 6-22. set_write_data_ready_delay()

// Function : set_write_data_ready_delay

// This will set the ready delays for each write data phase

// in a write data burst

function void set_write_data_ready_delay(axi_transaction trans);

for (int i = 0; i < trans.data_ready_delay.size(); i++)

trans.set_data_ready_delay(i, i);

endfunction

The set_read_data_valid_delay() function, when called, configures the RVALID signal to be

delayed by a number of ACLK cycles with the effect of delaying the start of each read data

phase (beat) in a read data burst. The starting point of the delay is determined by the

delay_mode operational transaction field (refer to “AXI3 BFM Delay Mode” on page 30 for

details).

For each read data phase (beat), the delay value of the RVALID signal is stored in an element of

the data_valid_delay[] array for the transaction, as demonstrated in Example 6-23.

You can edit this function to change the RVALID signal delay.

Example 6-23. set_read_data_valid_delay()

// Function : set_read_data_valid_delay

// This is used to set read response phase valid delays to start

// driving read data/response phases after specified delay.

function void set_read_data_valid_delay(axi_transaction trans);

for (int i = 0; i < trans.data_valid_delay.size(); i++)

trans.set_data_valid_delay(i, i);

endfunction

The set_wr_resp_valid_delay() function, when called, configures the BREADY signal

handshake to be delayed by a number of ACLK cycles, which extends the length of the write

response phase. The starting point of the delay is determined by the delay_mode operational

transaction field (refer to “AXI3 BFM Delay Mode” on page 30 for details). Example 6-24

below demonstrates setting the BREADY signal delay by 2 ACLK cycles. You can edit this

function to change the BREADY signal delay.

Example 6-24. set_wr_resp_valid_delay()

// Function : set_wr_resp_valid_delay

// This is used to set write response phase valid delay to start

// driving write response phase after specified delay.

function void set_wr_resp_valid_delay(axi_transaction trans);

trans.set_write_response_valid_delay(2);

endfunction

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