Altera IP Compiler for PCI Express Bedienungsanleitung PDF herunterladen (Seite 172)

7–8 Chapter 7: Reset and Clocks

Clocks

IP Compiler for PCI Express User Guide August 2014 Altera Corporation

The input clocks are used for the following functions:

■

refclk

— For generic PIPE PHY implementations,

refclk

is driven directly to

clk125_out

■

clk125_in

—This signal is the clock for all of the ×1 and ×4 IP core registers, except

for a small portion of the receive PCS layer that is clocked by a recovered clock in

internal PHY implementations. All synchronous application layer interface signals

are synchronous to this 125 MHz clock. In generic PIPE PHY implementations,

clk125_in

must be connected to the

pclk

signal from the PHY.

■

clk250_in

– This signal is the clock for all of the ×8 IP core registers. All

synchronous application layer interface signals are synchronous to this clock.

clk250_in

must be 250 MHz and it must be the exact same frequency as

clk250_out

100 MHz Reference Clock and 125 MHz Application Clock

When you configure an Arria GX, Arria II GX, Cyclone IV GX, HardCopy IV GX,

Stratix II GX, or Stratix IV GX device with a ×1 or ×4 variation, the 100 MHz clock is

connected directly to the transceiver. The

clk125_out

is driven by the output of the

transceiver.

The

clk125_out

must be connected back to the

clk125_in

input, possibly through a

clock distribution circuit required by the specific application. The user application

interface is synchronous to the

clk125_in

input.

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