Altera IP Compiler for PCI Express Bedienungsanleitung Seite 158
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6–10 Chapter 6: Register Descriptions
PCI Express Avalon-MM Bridge Control Register Content
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
Each entry in the PCI Express address translation table (Table 6–17) is 8 bytes wide,
regardless of the value in the current PCI Express address width parameter. Therefore,
register addresses are always the same width, regardless of IP Compiler for PCI
Express address width.
The format of the address space field (A2P_ADDR_SPACEn) of the address
translation table entries is shown in Table 6–18.
PCI Express to Avalon-MM Interrupt Status and Enable Registers
The registers in this section contain status of various signals in the PCI Express
Avalon-MM bridge logic and allow Avalon interrupts to be asserted when enabled. A
processor local to the system interconnect fabric that processes the Avalon-MM
interrupts can access these registers. These registers must not be accessed by the PCI
Express Avalon-MM bridge master ports; however, there is nothing in the hardware
that prevents this.
Table 6–17. Avalon-MM-to-PCI Express Address Translation Table Address Range: 0x1000-0x1FFF
Address Bits Name
Access
Description
0x1000
[1:0] A2P_ADDR_SPACE0 RW
Address space indication for entry 0. Refer to Table 6–18
for the definition of these bits.
[31:2] A2P_ADDR_MAP_LO0 RW
Lower bits of Avalon-MM-to-PCI Express address map
entry 0.
0x1004 [31:0] A2P_ADDR_MAP_HI0 RW
Upper bits of Avalon-MM-to-PCI Express address map
entry 0.
0x1008
[1:0] A2P_ADDR_SPACE1 RW
Address space indication for entry 1. Refer to Table 6–18
for the definition of these bits.
[31:2] A2P_ADDR_MAP_LO1 RW
Lower bits of Avalon-MM-to-PCI Express address map
entry 1.
This entry is only implemented if number of table entries
is greater than 1.
0x100C [31:0] A2P_ADDR_MAP_HI1 RW
Upper bits of Avalon-MM-to-PCI Express address map
entry 1.
This entry is only implemented if the number of table
entries is greater than 1.
Note to Table 6–17:
(1) These table entries are repeated for each address specified in the Number of address pages parameter (Table 3–14 on page 3–21). If Number
of address pages is set to the maximum of 512, 0x1FF8 contains A2P_ADDR_MAP_LO511 and 0x1FFC contains A2P_ADDR_MAP_HI511.
Table 6–18. PCI Express Avalon-MM Bridge Address Space Bit Encodings
Value
(Bits 1:0)
Indication
00
Memory Space, 32-bit PCI Express address. 32-bit header is generated.
Address bits 63:32 of the translation table entries are ignored.
01 Memory space, 64-bit PCI Express address. 64-bit address header is generated.
10 Reserved
11 Reserved
- User Guide 1
- IP Compiler for PCI Express 1
- 1. Datasheet 3
- 1–2 Chapter 1: Datasheet 4
- Features 4
- Release Information 5
- Device Family Support 6
- PCIe Hard IP Block 7
- FPGA Fabric 7
- Transceivers 7
- Notes to Table 1–5: 8
- Chapter 1: Datasheet 1–7 9
- 1–8 Chapter 1: Datasheet 10
- General Description 10
- IP Core Verification 11
- Simulation Environment 12
- Recommended Speed Grades 13
- 1–12 Chapter 1: Datasheet 14
- Notes to Table 1–9: 15
- 1–14 Chapter 1: Datasheet 16
- 2. Getting Started 17
- Using the Parameter Editor 19
- Modifying an IP Variation 20
- Upgrading Outdated IP Cores 20
- 0x00000000 24
- Viewing the Generated Files 26
- Simulating the Design 28
- Example 2-1 continued 30
- Constraining the Design 32
- Reusing the Example Design 36
- 3. Parameter Settings 37
- System Settings 38
- PCI Base Address Registers 38
- Notes to Table 3–2: 39
- Link Capabilities 40
- Error Reporting 40
- Buffer Configuration 41
- Avalon-MM Settings 42
- Address Translation 43
- IP Core Parameters 44
- PCI Registers 47
- Capabilities Parameters 49
- 31 19 18 17 16 15 14 51
- Buffer Setup 52
- Power Management 54
- Avalon-MM Configuration 56
- 4. IP Core Architecture 59
- Application Interfaces 60
- Crossing 62
- “64- or 128-Bit 63
- RX Datapath 64
- TX Datapath 64
- LMI Interface (Hard IP Only) 65
- Incremental Compilation 66
- Transaction Layer 67
- Configuration Space 69
- Data Link Layer 70
- Physical Layer 72
- Physical Layer Architecture 73
- PCI Express Avalon-MM Bridge 75
- Memory write requests 76
- Note to Figure 4–11: 80
- <n> ≤ 15)) 82
- Avalon-MM RX Master Block 85
- Interrupt Handler Block 85
- 5. IP Core Interfaces 87
- Notes to Figure 5–1: 88
- Notes to Figure 5–2: 89
- Notes to Figure 5–3: 90
- Note to Table 5–1: 91
- Notes to Table 5–2: 94
- (Note 1) 96
- Addresses 98
- Avalon-ST Interface 100
- Notes to Table 5–4: 103
- Note to Figure 5–16: 104
- Notes to Figure 5–17: 104
- Notes to Figure 5–18: 105
- <n> 107
- ECRC Forwarding 108
- IP implementation 109
- Reset Details 111
- _core.v or .vhd 112
- ECC Error Signals 113
- Status Register 114
- Note to Table 5–14: 119
- Table 5–14 120
- IP Compiler for 123
- PCI Express 123
- LMI Read Operation 124
- LMI Write Operation 124
- Power Management Signals 125
- Capabilities register 126
- Completion Side Band Signals 127
- ■ lmi_addr: 12'h81C 129
- ■ lmi_addr: 12'h820 129
- ■ lmi_addr: 12'h824 129
- ■ lmi_addr: 12'h828 129
- Notes to Figure 5–36: 130
- Note to Figure 5–37: 131
- Express 132
- RX Avalon-MM Master Signals 135
- Clock Signals 137
- Reset and Status Signals 137
- Note to figure 138
- Transceiver Control Signals 139
- Note to Table 5–28: 140
- Note to Table 5–29: 140
- Serial Interface Signals 141
- PIPE Interface Signals 142
- ■ 1'b0: -6 dB 143
- ■ 1'b1: -3.5 dB 143
- Test Signals 144
- Notes to Table 5–33: 146
- Avalon-ST Test Signals 148
- 6. Register Descriptions 149
- Note to Table 6–2: 150
- Note to Table 6–3: 151
- Note to Table 6–4: 151
- Note to Table 6–5: 152
- Note to Table 6–6: 152
- Note to Table 6–7: 152
- Note to Table 6–8: 153
- Note to Table 6–9: 154
- Note to Table 6–10: 154
- PCI Express Mailbox Registers 156
- Note to Table 6–17: 158
- Avalon-MM Mailbox Registers 159
- PCIe Spec Rev 2.0 160
- 7. Reset and Clocks 165
- Note to Figure 7–1: 166
- <variant>.v or .vhd 167
- <variant> 168
- <variant>_ 168
- Stratix IV GX Device 170
- User Application 170
- Note to Table 7–1: 171
- .v or .vhd 174
- Note (1) 174
- .v or .vhd - For Simulation 175
- Supported Message Types 177
- Notes to Table 8–1: 179
- Receive Buffer Reordering 180
- Notes to Table 8–2: 181
- 9. Optional Features 183
- ECRC on the TX Path 184
- Notes to Table 9–2: 185
- Exit Latency 186
- Acceptable Latency 186
- Source Multiple Tcl Scripts 189
- 10. Interrupts 191
- 10–2 Chapter 10: Interrupts 192
- MSI Interrupts 192
- Legacy Interrupts 193
- 10–4 Chapter 10: Interrupts 194
- Chapter 10: Interrupts 10–5 195
- 10–6 Chapter 10: Interrupts 196
- 11. Flow Control 197
- 11–2 Chapter 11: Flow Control 198
- Throughput of Posted Writes 198
- Chapter 11: Flow Control 11–3 199
- Notes to Table 11–1: 200
- Chapter 11: Flow Control 11–5 201
- 11–6 Chapter 11: Flow Control 202
- 12. Error Handling 203
- Physical Layer Errors 204
- Data Link Layer Errors 204
- Transaction Layer Errors 205
- Note to Table 12–4: 207
- Cancellation 211
- Dynamic Reconfiguration 212
- 14. External PHYs 221
- External PHY Support 222
- 8-bit DDR Mode 223
- 8-bit SDR Mode 225
- 16-bit PHY Interface Signals 227
- 8-bit PHY Interface Signals 229
- Selecting an External PHY 230
- August 2014 233
- Endpoint Testbench 234
- Chaining DMA 235
- Root Port Testbench 236
- Chaining DMA Design Example 238
- Root Complex 240
- IP Compiler 240
- <variant>_plus 241
- Note to Table 15–5: 246
- Note to Table 15–7: 247
- Test Driver Module 250
- DMA Write Cycles 251
- DMA Read Cycles 253
- Root Port Design Example 254
- Root Port BFM 258
- BFM Memory Map 260
- Figure 15–8 264
- BFM Procedures and Functions 266
- BFM Configuration Procedures 271
- Shared Memory Constants 273
- Log Constants 275
- VHDL Formatting Functions 278
- 16. Qsys Design Example 289
- Creating a Quartus II Project 290
- Running Qsys 291
- Filter Icon 296
- Note to Table 16–11: 298
- Generating the Qsys System 300
- Simulating the Qsys System 301
- Running Simulation 303
- Design Example Wrapper File 305
- Compiling the Design 307
- Programming a Device 307
- 17. Debugging 309
- 17–2 Chapter 17: Debugging 310
- Hardware Bring-Up Issues 310
- Use Third-Party PCIe Analyzer 311
- 17–4 Chapter 17: Debugging 312
- Link and Transceiver Testing 312
- A–2 Chapter : 314
- Notes to Table A–8: 315
- A–4 Chapter : 316
- Chapter : A–5 317
- A–6 Chapter : 318
- Descriptor/Data Interface 319
- Notes to Figure B–2: 320
- Chapter : B–3 321
- B–4 Chapter : 322
- Refer to Table B–3 323
- Note to Table B–4: 324
- Descriptor 325
- Signals 327
- B–12 Chapter : 330
- Note to Table B–6: 331
- Note to Table B–7: 332
- Note to Table B–8: 333
- for the ×8 IP cores 334
- DW 1 DW 3 338
- DW 5 DW 7 338
- DW 0 DW 2 DW 4 DW 6 338
- 12345678 910111213 338
- DW 0DW 2DW 4 339
- DW 1DW 3DW 5DW 7 339
- 12345678 9 339
- B–24 Chapter : 342
- Chapter : B–25 343
- Notes to Table B–11: 344
- ICM Features 345
- ICM Functional Description 345
- Note to Table B–12: 346
- ICM Block Diagram 347
- ICM Files 348
- Chapter : B–31 349
- RX Ports 350
- Chapter : B–33 351
- B–34 Chapter : 352
- 2345678 91011121314 353
- Sideband Interface 354
- Soft IP Implementation 355
- Arria II GX Devices 356
- Stratix II GX Devices 356
- Avalon-MM Interface 357
- Cyclone III Family 359
- Stratix III Family 360
- Stratix IV Family 360
- Additional Information 361
- Info–2 Chapter : 362
- Revision History 362
- 256-bit interface 363
- Simulation support 363
- Info–4 Chapter : 364
- Chapter : Info–5 365
- Info–6 Chapter : 366
- Chapter : Info–7 367
- Info–8 Chapter : 368
- Chapter : Info–9 369
- How to Contact Altera 370
- Typographic Conventions 370
- Chapter : Info–11 371
- Info–12 Chapter : 372
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