Altera IP Compiler for PCI Express Bedienungsanleitung PDF herunterladen (Seite 106)

5–20 Chapter 5: IP Core Interfaces

Avalon-ST Interface

IP Compiler for PCI Express User Guide August 2014 Altera Corporation

Figure 5–21 shows the mapping of 128-bit Avalon-ST TX packets to PCI Express TLPs

for a 3 dword header with non-qword aligned addresses.

Figure 5–22 shows the mapping of 128-bit Avalon-ST TX packets to PCI Express TLPs

for a four dword header TLP with qword aligned data.

Figure 5–23 shows the mapping of 128-bit Avalon-ST TX packets to PCI Express TLPs

for a four dword header TLP with non-qword aligned addresses. In this example,

tx_st_empty

is low because the data ends in the upper 64 bits of

tx_st_data

Figure 5–21. 128-Bit Avalon-ST tx_st_data Cycle Definition for 3-DWord Header TLP with non-QWord Aligned Address

clk

tx_st_valid

tx_st_data[127:96]

tx_st_data[95:64]

tx_st_data[63:32]

tx_st_data[31:0]

tx_st_sop

tx_st_err

tx_st_eop

tx_st_empty

Data0 Data 4

Header 2

Data 3

Header 1 Data 2

Data (n)

Header 0 Data 1

Data (n-1)

Figure 5–22. 128-Bit Avalon-ST tx_st_data Cycle Definition for 4-DWord Header TLP with QWord Aligned Address

clk

tx_st_data[127:96]

tx_st_data[95:64]

tx_st_data[63:32]

tx_st_data[31:0]

tx_st_sop

tx_st_eop

tx_st_empty

Header 3 Data 3

Header 2 Data 2

Header 1 Data 1

Header 0 Data 0 Data 4

Figure 5–23. 128-Bit Avalon-ST tx_st_data Cycle Definition for 4-DWord Header TLP with non-QWord Aligned Address

Header 3 Data 2

Header 2 Data 1

Data n

Header 1 Data 0

Data n-1

Header 0

Data n-2

clk

tx_st_valid

tx_st_data[127:96]

tx_st_data[95:64]

tx_st_data[63:32]

tx_st_data[31:0]

tx_st_sop

tx_st_eop

tx_st_empty

1 2 ... 101 102 103 104 105 106 107 108 109 110 111 ... 371 372

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