Altera Interlaken MegaCore Function Bedienungsanleitung Seite 75
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Appendix B: Excluding Transceivers for Faster Simulation B–3
External Transceiver Interface Clocks
June 2012 Altera Corporation Interlaken MegaCore Function
User Guide
1 For all Interlaken MegaCore variations except the 8-lane, 3.125-Gbps variation, Altera
recommends that the same clock drive the
rx_mac_c_clk
,
tx_mac_c_clk
, and
tx_lane_c_clk
clocks.
Because the Interlaken MegaCore function does not include the high-speed
transceivers in this case, the
ref_clk
and
cal_blk_clk
input clocks to the transceivers,
which are input signals to the Interlaken MegaCore function if it includes
transceivers, are not included in the MegaCore function that excludes transceivers.
The reset controller is excluded from these variations because it runs on the
cal_blk_clk
clock, which is not available.
Figure B–2 illustrates how you can derive the external transceiver interface signal and
clock information by simply removing the HSIO banks from the corresponding
variation with transceivers. Figure B–3 and Figure B–4 show the four-lane and
eight-lane variations without transceivers.
Figure B–3 shows the clock diagram for a four-lane variation that does not include
transceivers.
Figure B–2. Clock Diagram for 4-lane Interlaken MegaCore Function with Transceivers
cal_blk_clk
ref_clk
clk_in
tx_datain[79:0]
clk_out (master TX clock)
common_rx_clk
rx_dataout[79:0]
rx_clk[3:0]
tx_pin[3:0]
rx_pin[3:0]
tx_lane_clk
tx_data [79:0]
rx_data [79:0]
rx_lane_clk [3:0]
common_rx_coreclk
HSIO Bank 0
(low latency PCS mode)
tx_coreclkout
rx_coreclkout
x4
tx_mac_clk
rx_mac_clk
TX MAC and PCS
Exposed Interface to Transceivers
RX MAC and PCS
Figure B–3. Clock Diagram for 4-lane Interlaken MegaCore Function Without Transceivers
tx_lane_clk
tx_data[79:0]
rx_data[79:0]
rx_lane_clk[3:0]
common_rx_coreclk
Interlaken
MegaCore Function
tx_mac_clk
rx_mac_clk
- User Guide 1
- Interlaken MegaCore Function 1
- Contents 3
- Chapter 5. Signals 4
- Contents v 5
- Features 7
- Device Family Support 8
- MegaCore Verification 9
- Release Information 10
- Installation and Licensing 10
- OpenCore Evaluation 12
- 2. Getting Started 13
- Qsys Design Flow Summary 14
- Qsys Design Flow 16
- Specifying Parameters 17
- Completing the Qsys System 18
- Simulating the System 18
- Specifying Constraints 19
- I/O Standard Constraints 20
- 3. Parameter Settings 23
- Lane Rate 24
- Number of Words in Meta Frame 24
- Exclude Transceiver 24
- Burst Parameters 25
- 4. Functional Description 27
- Architecture Overview 28
- Interfaces Overview 28
- Note to Table 4–1: 29
- Avalon-ST Interface 30
- Clocking and Reset Structure 31
- MAC Clock Verified Frequency 35
- PCS Clock Frequencies 36
- Transmit Path 37
- Receive Path 43
- Channel Filtering Blocks 45
- Packet Regrouper 45
- Calendar and Status Block 46
- Lane Status Block 47
- High-Speed I/O Block 48
- Transceivers 49
- 5. Signals 53
- Exclude transceivers 54
- Chapter 5: Signals 5–3 55
- Note to Table 5–2: 56
- Note to Table 5–3: 56
- Application Interface Signals 57
- Note to Table 5–6: 58
- Chapter 5: Signals 5–7 59
- Note to Table 5–8: 60
- Note to Table 5–9: 61
- Note to Table 5–10: 61
- Note to Table 5–11: 62
- Note to Table 5–12: 62
- Transceiver Banks 63
- Running a Design Example 65
- Setting Up the Design Example 66
- Function 69
- Simulation 73
- Reset Signals 79
- Required Reset Sequence 80
- Additional Information 87
- Typographic Conventions 88
- Visual Cue Meaning 89
- Info–4 Additional Information 90
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