Altera High-Speed Development Kit, Stratix GX Edition Bedienungsanleitung PDF herunterladen (Seite 92)

7–10 Quartus II Version 3.0 Altera Corporation

Standard Tests High-Speed Development Kit, Stratix GX Edition User Guide

Figure 7–5. Stratix GX Top-Level BDF

Figure 7–6. Stratix Top-Level BDF

The system clock is generated by an enhanced PLL using the on-board

33.33-MHz crystal oscillator as the reference clock. The PLL generates a

105-MHz clock to clock all of the data generation logic and serve as the

reference for the LVDS transmitter on the Stratix GX device.

1 2 ... 87 88 89 90 91 92 93 94 95 96 97 ... 139 140

Keine Kommentare

Altera High-Speed Development Kit, Stratix GX Edition Bedienungsanleitung Seite 92