Altera Arria II GX FPGA Bedienungsanleitung PDF herunterladen (Seite 4)

iv Contents

Arria II GX FPGA Development Kit User Guide February 2011 Altera Corporation

Erase ..............................................................................6–9

Flash Memory Map .................................................................6–9

The SSRAM Tab .....................................................................6–10

Read .............................................................................6–10

Write ............................................................................6–11

Random Test ......................................................................6–11

Increment Test ....................................................................6–11

The DDR3 Tab .......................................................................6–11

Start .............................................................................6–12

Stop .............................................................................6–12

Performance Indicators .............................................................6–12

Error Control .....................................................................6–12

Number of Addresses to Write/Read ................................................6–12

Data Type ........................................................................6–12

W/R Control ......................................................................6–13

The DDR2 Tab .......................................................................6–13

Start .............................................................................6–14

Stop .............................................................................6–14

Performance Indicators .............................................................6–14

Error Control .....................................................................6–14

Number of Addresses to Write/Read ................................................6–14

Data Type ........................................................................6–14

W/R Control ......................................................................6–15

The HSMC Tab ......................................................................6–15

Status ............................................................................6–16

Port ..............................................................................6–16

PMA Setting ......................................................................6–16

Data Type ........................................................................6–16

Error Control .....................................................................6–17

Start .............................................................................6–17

Stop .............................................................................6–17

Performance Indicators .............................................................6–17

The Power Monitor .....................................................................6–18

General Information ...............................................................6–19

Power Information .................................................................6–19

Power Graph ......................................................................6–19

Graph Settings ....................................................................6–19

Reset .............................................................................6–19

Calculating Power ...................................................................6–20

Configuring the FPGA Using the Quartus II Programmer ....................................6–20

Appendix A. Programming the Flash Memory Device

CFI Flash Memory Map ................................................................. A–1

Preparing Design Files for Flash Programming ............................................. A–2

Creating Flash Files Using the Nios II EDS .............................................. A–2

Programming Flash Memory Using the Board Update Portal ................................. A–3

Programming Flash Memory Using the Nios II EDS ......................................... A–3

Restoring the Flash Device to the Factory Settings .......................................... A–4

Restoring the MAX II CPLD to the Factory Settings ......................................... A–5

Additional Information

Document Revision History ........................................................... Info–1

How to Contact Altera ................................................................ Info–1

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