Altera Arria II GX FPGA Bedienungsanleitung PDF herunterladen (Seite 26)

6–6 Chapter 6: Board Test System

Using the Board Test System

Arria II GX FPGA Development Kit, 6G Edition User Guide July 2010 Altera Corporation

■ PSO—Sets the MAX II PSO register. The following options are available:

■ Use PSR—Allows the PSR to determine the page of flash memory to use for

FPGA reconfiguration.

■ Use PSS—Allows the PSS to determine the page of flash memory to use for

FPGA reconfiguration.

■ PSR—Sets the MAX II PSR register. The numerical values in the list corresponds to

the page of flash memory to load during FPGA reconfiguration. Refer to Table 6–1

for more information.

■ PSS—Displays the MAX II PSS register value. Refer to Table 6–1 for the list of

available options.

■ OCR1—Sets the MAX II OCR1 register. Refer to Table 6–1 for the list of available

options.

■ SRST—Resets the system and reloads the FPGA with a design from flash memory

based on the other MAX II register values. Refer to Table 6–1 for more information.

1 Because the Config tab requires that a specific design is running in the FPGA at a

specific clock speed, writing a 0 to SRST; writing a 1, 2, or 3 to OCR2; or changing the

PSO value can cause the Board Test System to stop running.

JTAG Chain Devices

The JTAG chain devices control shows all the devices currently in the JTAG chain.

The Arria II GX device is always the first device in the chain.

1 Uninstalling the shunt jumper from jumper J9 pins 1-2 includes the MAX II device in

the JTAG chain.

Flash Memory Map

The Flash memory map control shows the memory map of the flash memory device

on your board.

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Altera Arria II GX FPGA Bedienungsanleitung Seite 26