Altera ALTPLL (Phase-Locked Loop) IP Core Bedienungsanleitung PDF herunterladen (Seite 52)

DescriptionTypeParameter

Specifies the high period count for the corresponding

L[1..0] counter. Values range from 1 to 512. If omitted,

the default is 1.

IntegerL[]_HIGH

Specifies the initial value for the corresponding L[1..0]

counter. Values range from 1 to 512. If omitted, the default

is 1.

IntegerL[]_INITIAL

Specifies the low period count for the corresponding

L[1..0] counter. Values range from 1 to 512. If omitted,

the default is 1.

IntegerL[]_LOW

Specifies the mode for the corresponding L[1..0] counter.

Values are BYPASS, ODD or EVEN. If omitted, the default is

BYPASS.

StringL[]_MODE

Specifies the phase tap for the corresponding L[1..0]

counter. Values range from 0 to 7. If omitted, the default

is 0.

IntegerL[]_PH

Specifies, in nanoseconds (ns), the time delay for the

corresponding L[1..0] counter. Values range from 0 ns

to 3 ns. If omitted, the default is 0.

StringL[]_TIME_DELAY

Specifies the number of half-clock cycles that the output

clocks must be locked before the locked port goes high.

This parameter is required for simulation in third-party

simulators. Available for Stratix IV, Stratix III, Cyclone IV,

and Cyclone III devices only.

IntegerLOCK_HIGH

Specifies the number of half-clock cycles that the output

clocks must be out-of-lock before the locked port goes

low. This parameter is required for simulation in third-

party simulators. Available for Stratix IV, Stratix III,

Cyclone IV, and Cyclone III devices only.

IntegerLOCK_LOW

Specifies the value of the LOCK_WINDOW_UI setting. If

omitted, default is 0.05.

StringLOCK_WINDOW_UI

Specifies, in picofarads (pF), the value of the loop capacitor.

Values range from 5 to 20 pF. The Compiler cannot achieve

all values. If omitted, the default value is 10.

StringLOOP_FILTER_C

Specifies, in kilo ohms (K Ohm), the value of the loop

resistor. Values range from 1 K to 20 K. The Compiler

cannot achieve all values.

StringLOOP_FILTER_R

Allows you to specify Altera-specific parameters in VHDL

Design Files (.vhd). The default is UNUSED.

StringLPM_HINT

Identifies the library of parameterized modules (LPM)

entity name in VHDL Design Files.

StringLPM_TYPE

ALTPLL (Phase-Locked Loop) IP Core User Guide

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ALTPLL Parameters

2014.08.18

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