Altera ALTDQ_DQS2 Bedienungsanleitung Seite 86
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Dynamic Configuration
At 100 ns, there is a high pulse on the beginscan signal. When the agent_output_enable signal is pulled
low, the strobe_io and agent_dqs_in goes to Hi-Z between 110 ns and 8.795 us time mark, some
internal calibration is being carried out. Dynamic configuration is the main feature used. At 8.795 us time
mark, the enable_driver signal is asserted. This specifies that the internal calibration is completed, and
the control is passed on to the host controller (the DQS driver) to perform the normal read/write
operation.
Note: For RTL related to dynamic configuration operations in this design example, refer to
config_controller.sv file.
You can override the static values at runtime with a scan chain using the dynamic configuration feature in
the ALTDQ_DQS2 IP core. To help you achieve static timing closure, the dynamic configuration feature
allows you to override the static values at runtime with a scan chain. Each I/O and the DQS logic contain
its own scan chain block (shift registers). This section shows you how to serially scan configuration bits
into each scan chain block, between 100 ns and 8.795 us time mark.
The following figure shows the waveform for the dynamic configuration simulation generated after
executing topwave.do (located in the simulation/modelsim folder), between the high pulses of
beginscan and scandone.
Figure 56: Dynamic Configuration Waveform
Because the enable_driver signal is asserted at 8.795 us time mark, following read and write operations
will be executed by DQS driver.
Note:
The driver_clk is running at the same rate as the core
Related Information
• Dynamic Reconfiguration for ALTDQ_DQS2 on page 38
DQS Write Operation
The driver asserting the dqs_enable signal at 8.925 µs begins the write operation. This will configure the
ALTDQ_DQS2’s output_strobe_ena to high, getting ready to send out strobe to the DQS agent. The
dqs_write signal is asserted at 8.935 µs. This sets the write_oe_in signal of the ALTDQ_DQS2 IP core to
high, getting ready to send out data to the DQS agent. The data are written to the dqs_writedata of the
DQS driver, and then reflected in the dq signal of the ALTDQ_DQS2 IP core. The data written out from
the DQS driver is also stored in checkfifo. During the DQS write operation, the strobe_io and
agent_dqs_in is toggling. Dqs_write deasserts at 8.985 us and dqs_enable deasserts at 8.995 us.
Outgoing data from the dq signal of the ALTDQ_DQS2 IP core is center-aligned to the strobe
(strobe_io).
86
Dynamic Configuration
UG-01089
2014.12.17
Altera Corporation
ALTDQ_DQS2 IP Core User Guide
Send Feedback
- ALTDQ_DQS2 IP Core User Guide 1
- Related Information 2
- Using the Parameter Editor 4
- Adding IP Cores to IP Catalog 4
- Changes search path order 5
- Figure 5: IP Parameter Editor 7
- Upgrading IP Cores 8
- ALTDQ_DQS2 Parameter Settings 11
- Altera recommends using 12
- UG-01089 13
- 2014.12.17 13
- ALTDQ_DQS2 Data Paths 17
- Altera Corporation 18
- Send Feedback 18
- Block Name Description 19
- FIFO Control 21
- DQ and DQS Output Path 22
- ALTDQ_DQS2 Ports 24
- ALTDQ_DQS2 Data Strobe Ports 26
- ALTDQ_DQS2 Data Ports 29
- Port Name Type Width 30
- Description 30
- ALTDQ_DQS2 PLL and DLL Ports 33
- ALTDQ_DQS2 Hard FIFO Ports 34
- Ports Type Width Description 35
- Max Value Inc. Unit 50
- Stratix V Design Example 59
- Instantiating ALT_OCT IP Core 61
- Instantiating Altera PLL 62
- Clock Description 63
- Component Description 66
- Dynamic Configuration 67
- DQS Delay Chain 70
- Hard Read FIFO 71
- Implement as Soft FIFOs 72
- SDC Walkthrough 73
- Arria V Design Example 77
- VFIFO, LFIFO, and Read FIFO 89
- DQS Enable Control 91
- Analyzing Same Edge Transfer 93
- Timing Violation 95
- IP-Generate Command 96
- Document Revision History 97
- Date Version Changes 100
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