Altera PHY IP Core Betriebsanweisung

Arria 10 Transceiver PHY User GuideSubscribeSend FeedbackUG-011432015.05.11101 Innovation DriveSan Jose, CA 95134www.altera.com

Figure 1-2: Arria 10 GX Devices with 96 Transceiver Channels and Four PCIe Hard IP BlocksTransceiverBankTransceiverBankTransceiverBankGXBL1JTransceive

Name Direction Clock Domain Descriptionunused_tx_parallel_dataInputtx_clkout This signal specifies the unused data when you turnon Enable simplified d

Name Direction Clock Domain Descriptionrx_coreclkin Input ClockRX parallel clock that drives the read side clock ofthe RX FIFO.Table 2-62: TX and RX F

Name Direction Clock Domain Descriptionrx_std_rmfifo_empty[<n>-1:0]Output Asynchronous Rate match FIFO empty flag. When asserted, matchFIFO is e

Name Direction Clock Domain Descriptionrx_errdetect[<n><w>/<s>-1:0]OutputSynchronousto the clockdriving theread side ofthe FIFO (rx_

Name Direction Clock Domain Descriptiontx_std_bitslipboun-darysel[5 <n>-1:0]InputAsynchronous Bitslip boundary selection signal. Specifies thenu

Table 2-66: Bit Reversal and Polarity InversionName Direction ClockDomainDescriptionrx_std_byterev_ena[<n>-1:0]Input Asynchro‐nousThis control s

IP Core File LocationsWhen you generate your Transceiver Native PHY IP, the Quartus® II software generates the HDL filesthat define your instance of t

Table 2-67: Transceiver Native PHY Files and DirectoriesFile Name Description<project_dir> The top-level project directory.<your_ip_name>

Interlaken operates on 64-bit data words and 3 control bits, which are striped round-robin across thelanes. The protocol accepts packets on 256 logica

Related Information• Interlaken Protocol Definition v1.2• Interlaken Look-Aside Protocol Definition, v1.1Metaframe Format and Framing Layer Control Wo

Figure 1-3: Arria 10 GX Devices with 72 and 48 Transceiver Channels and Four PCIe Hard IP Blocks.TransceiverBankTransceiverBankTransceiverBankTranscei

The DIAG word is comprised of a status field and a CRC-32 field. The 2-bit status is defined by theInterlaken specification as:• Bit 1 (Bit 33): Lane

Because of xN clock network skew, the maximum achievable data rate decreases when TX channels spanseveral transceiver banks.Figure 2-15: 10X12.5 Gbps

network. In feedback compensation bonding, the separate x6 clocks are in phase and frequency alignedwith each other. One PLL from each transceiver ban

TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State MachineThe Interlaken configuration sets the enhanced PCS TX and RX FIFOs in Interlaken

Figure 2-17: TX Soft Bonding FlowExit fromtx_digitalresetDeassert all lanes tx_enh_frame_burst_enAssert all lanes tx_enh_data_validDeassert all lanes

Figure 2-18: TX FIFO Pre-fill (6-lane Interface)tx_enh_data_validtx_digitalresettx_enh_fifo_fulltx_enh_fifo_pfulltx_enh_fifo_emptytx_enh_fifo_pemptytx

Implement a multi-lane alignment deskew state machine to control the RX FIFO operation based onavailable RX FIFO status flags and control signals.Figu

Figure 2-21: RX FIFO Deskewrx_enh_data_validrx_enh_fifo_rd_enrx_enh_fifo_fullrx_enh_fifo_pfullrx_enh_fifo_emptyrx_enh_fifo_pemptyrx_enh_fifo_align_val

Figure 2-22: Signals and Ports of Native PHY IP for Interlakenreconfig_resetreconfig_clkreconfig_avmmtx_digital_resettx_clkouttx_coreclkintx_control[1

7. Implement a TX soft bonding logic and an RX multi-lane alignment deskew state machine using fabriclogic resources for multi-lane Interlaken impleme

Figure 1-4: Arria 10 GX Devices with 66 Transceiver Channels and Three PCIe Hard IP BlocksTransceiverBankTransceiverBankGXBL1HTransceiverBankGXBL1GTra

Figure 2-24: 24 Lanes Bonded Interlaken Link, TX DirectionTo show more details, three different time segments are shown with the same zoom level.24`h0

• Resetting Transceiver Channels on page 4-1Reset controller general information and implementation details• Enhanced PCS Ports on page 2-54For detail

Parameter ValueProvide separate interface for eachchannelOn / OffTable 2-69: TX PMA ParametersParameter ValueTX channel bonding mode Not bondedPMA-onl

Parameter ValueEnable rx_seriallpbken port On / OffTable 2-70: RX PMA ParametersParameter ValueNumber of CDR reference clocks 1 to 5Selected CDR refer

Table 2-71: Enhanced PCS ParametersParameter ValueEnhanced PCS / PMA interface width 32, 40, 64FPGA fabric / Enhanced PCS interfacewidth67Enable &apos

Parameter ValueEnable rx_enh_fifo_pempty port On / OffEnable rx_enh_fifo_del port(10GBASE-R)OffEnable rx_enh_fifo_insert port(10GBASE-R)OffEnable rx_e

Parameter ValueEnable rx_enh_frame_diag_status port On / OffTable 2-74: Interlaken CRC-32 Generator and Checker ParametersParameter ValueEnable Interl

Table 2-77: Block Sync ParametersParameter ValueEnable RX block synchronizer OnEnable rx_enh_blk_lock port On / OffTable 2-78: Gearbox ParametersParam

Parameter ValueGenerate SystemVerilog package file On / OffGenerate C header file On / OffGenerate MIF (Memory IntializationFile)On / OffTable 2-81: G

Figure 2-26: GbE PHY Connection to IEEE 802.3 MAC and RSApplicationPresentationSessionTransportNetworkData LinkPhysicalOSIReferenceModelLayersHigher L

Figure 1-5: Arria 10 GX Devices with 48, 36, and 24 Transceiver Channels and Two PCIe Hard IP BlocksTransceiverBankTransceiverBankGXBL1ITransceiverBan

Figure 2-27: Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE, GbE with IEEE 1588v2RX FIFO (1)ByteDeserializer (4)8B/10B DecoderRate Mat

8B/10B Encoding for GbE, GbE with IEEE 1588v2The 8B/10B encoder clocks 8-bit data and 1-bit control identifiers from the transmitter phasecompensation

Figure 2-29: Reset Conditionclocktx_parallel_datatx_digitalresetK28.5K28.5K28.5K28.5xxxDx.yDx.yK28.5K28.5 K28.5Dx.y Dx.y Dx.ynn + 1n + 2n + 3n + 4Auto

Figure 2-30: rx_syncstatus HighThree Consecutive Ordered Sets Received to Achieve Synchronizationc5 bc 50 bcbc 50 8d8c 00 8c 8drx_parallel_datarx_data

Related Information8B/10B Decoder on page 5-50Rate Match FIFO for GbEThe rate match FIFO compensates frequency Part-Per-Million (ppm) differences betw

The rate match FIFO does not delete code groups to overcome a FIFO full condition. It asserts therx_std_rmfifo_full flag for at least two recovered cl

Before you beginYou should be familiar with the Standard PCS and PMA architecture, PLL architecture, and the resetcontroller before implementing the G

You can use your own reset controller or use the Native PHY Reset Controller IP core.7. Connect the Native PHY IP to the PLL IP and the reset controll

Table 2-83: General and Datapath OptionsThe first two sections of the Native PHY [IP] parameter editor for the Native PHY IP provide a list of general

Parameter ValueEnable tx_pma_rxfound port (QPI) On/OffEnable rx_seriallpbken port On/OffTable 2-85: RX PMA ParametersParameter ValueNumber of CDR refe

Figure 1-6: Arria 10 GX Devices with 12 Transceiver Channels and One PCIe Hard IP BlockTransceiverBankGXBL1DTransceiverBankGXBL1CTransceiverBankTransc

Parameters ValueFPGA fabric / Standard RX PCS interface width 10TX FIFO modelow latency (for GbE)register_fifo (for GbE with IEEE 1588v2)RX FIFO model

Parameters ValueRX word aligner mode Synchronous state machineRX word aligner pattern length 7, 10RX word aligner pattern (hex)0x000000000000007c (Com

The 10GBASE-R parallel data interface is the 10 Gigabit Media Independent Interface (XGMII) thatinterfaces with the Media Access Control (MAC), which

Figure 2-39: Transceiver Channel Datapath and Clocking for 10GBASE-RTransmitter Enhanced PCSTransmitter PMAReceiver PMAReceiver Enhanced PCSTXGearboxt

• Data acquisition• Test equipment• MeasurementThe protocol is applicable to systems communicating by local area networks including, but not limited t

The RX FEC sublayer:• Receives data from the PMA• Performs descrambling• Achieves FEC framing synchronization• Decodes and corrects data where necessa

Figure 2-42: Clock Generation and Distribution for 10GBASE-R with FEC SupportExample using a 64-bit PCS-PMA interface width.TX PLL64TX PMATX PCSTX64 B

Figure 2-43: XGMII Interface (DDR) and Transceiver Interface (SDR) for 10GBASE-R ConfigurationsD0TXD/RXD[31:0] D1 D2 D3 D4 D5 D6C0TXC/RXC[3:0] C1 C2 C

Related InformationArria 10 Enhanced PCS Architecture on page 5-18For more information about the Enhanced PCS ArchitectureHow to Implement 10GBASE-R,

Figure 2-44: Signals and Ports of Native PHY IP Core for the 10GBASE-R, 10GBASE-R with IEEE 1588v2,and 10GBASE-R with FECGenerating the IP core create

Arria 10 GT Device Transceiver LayoutThe largest GT device has 96 transceiver channels and four PCI Express Hard IP blocks. All GT deviceshave a total

Figure 2-45: Connection Guidelines for a 10GBASE-R or 10GBASE-R with FEC PHY DesignReset ControllerArria 10 Transceiver Native PHY To MAC/RSthrough X

Native PHY IP Parameter Settings for 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-Rwith FECTable 2-87: General and Datapath ParametersThe first

Parameter RangeSelected CDR reference clockfrequency322.265625 MHz and 644.53125 MHzPPM detector threshold62.5, 100,125, 200, 250, 300, 500, 1000CTLE

Parameter RangeEnable TX sync header error insertion OnOffTable 2-92: Scrambler and Descrambler ParametersParameter RangeEnable TX scrambler (10GBASE-

Parameter RangeEnable embedded JTAG AVMMmasterOnOffTable 2-96: Configuration Files ParametersParameter RangeConfiguration file prefix—Generate SystemV

Figure 2-48: Block Lock AssertionThis figure shows the assertion on rx_enh_blk_lock signal when the Receiver detects the blockdelineation.070707070707

10GBASE-KR PHY IP CoreThe 10GBASE-KR Ethernet PHY IP core supports the following features of Ethernet standards:• Auto negotiation for backplane Ether

The following table shows the typical expected resource utilization for selected configurations using theQuartus II software v15.0 for Arria 10 device

The 10GBASE-KR PHY IP core includes the following components:Standard and Enhanced PCS DatapathsThe Enhanced PCS and PMA inside the Native PHY are con

Figure 2-53: Reconfiguration Block DetailsPCSControllerTX EQ ControllerDFE ControllerCTLE ControllerPMA Controllerrcfg_datarcfg_datarcfg_data(1)rcfg_d

Note: Refer to Arria 10 GT Channel Usage on page 2-313 for details on Arria 10 GT channel usagerestrictions.Figure 1-9: Arria 10 GT Devices with 72 Tr

Related Information• 10GBASE-R Parameters on page 2-130• 10GBASE-KR Auto-Negotiation and Link Training Parameters on page 2-131General OptionsThe Gene

Parameter Name Options DescriptionEnable rx_clkout port OnOffWhen you turn on this parameter, the rx_clkout port is enabled. Refer to the clock andres

Table 2-102: FEC OptionsParameter Name Options DescriptionInclude FEC sublayer OnOffWhen you turn on this parameter, the coreincludes logic to impleme

10GBASE-KR Optional ParametersTable 2-104: Optional ParametersIn the following table, the exact correspondence between numerical values and voltages i

Name Value DescriptionINITMAINVAL Init VOD tapValue0-31 Specifies the initial VOD value. This value is set bythe Initialize command of the link traini

Clock and Reset InterfacesTable 2-105: Clock and Reset SignalsSignal Name Direction Descriptiontx_serial_clk_10g Input High speed clock from the 10G P

Signal Name Direction Descriptionrx_analogreset Input Resets the analog RX portion of the transceiverPHY. Synchronous to mgmt_clk.rx_digitalreset Inpu

Signal Name Direction Clock Domain Descriptionxgmii_rx_clkInputClock signalClock for SDR XGMII RX interface to the MAC. Thisclock can be connected to

Signal Name XGMII Signal Name Descriptionxgmii_rx_dc[8] xgmii_sdr_ctrl[0] Lane 0 controlxgmii_rx_dc[16:9] xgmii_sdr_data[15:8] Lane 1 dataxgmii_rx_dc[

Signal Name Direction Clock Domain Descriptionled_anOutputSynchronous to rx_clkoutClause 37 Auto-negotiation status. The PCSfunction asserts this sign

Figure 1-10: Arria 10 GT Devices with 48 Transceiver Channels and Two PCIe Hard IP BlocksTransceiverBankTransceiverBankTransceiverBankTransceiverBankT

Signal Name Direction Clock Domain Descriptionstart_pcs_reconfigInput Synchronous to mgmt_clkWhen asserted, initiates reconfiguration of thePCS. Sampl

10GBASE-KR PHY Register DefinitionsThe Avalon-MM slave interface signals provide access to the control and status registers.The following table specif

Table 2-113: 10GBASE-KR Register DefinitionsWord Addr Bit R/W Name Description0x4B00RW Reset SEQ When set to 1, resets the 10GBASE-KR sequencer(auto r

Word Addr Bit R/W Name Description0x4B10R SEQ Link Ready When asserted, the sequencer is indicating that thelink is ready.1 R SEQ AN timeout When asse

Word Addr Bit R/W Name Description0x4C00RW AN enable When set to 1, enables Auto Negotiation function.The default value is 1. For additional informati

Word Addr Bit R/W Name Description0x4C21RO AN page received When set to 1, a page has been received. When 0, apage has not been received. The current

Word Addr Bit R/W Name Description0x4C28 RO FEC negotiated –enable FEC from SEQWhen set to 1, PHY is negotiated to perform FEC.When set to 0, PHY is n

Word Addr Bit R/W Name Description0x4C315:0RW User base page low The Auto Negotiation TX state machine uses thesebits if the Auto Negotiation base pag

Word Addr Bit R/W Name Description0x4C5 15:0 RW User Next page low The Auto Negotiation TX state machine uses thesebits if the AN Next Page control bi

Word Addr Bit R/W Name Description0x4C9 15:0 RO LP Next page low The AN RX state machine receives these bits fromthe link partner. The following bits

In GT devices that have transceivers on both sides of the device, the GX transceiver channels on the rightside can be used in reduced power mode. In G

Word Addr Bit R/W Name Description0x4D00RW Link TrainingenableWhen 1, enables the 10GBASE-KR start-upprotocol. When 0, disables the 10GBASE-KR start-u

Word Addr Bit R/W Name Description0x4D014:12RW equal_cnt [2:0]Adds hysteresis to the error count to avoid localminimums. The following values are defi

Word Addr Bit R/W Name Description0x4D019:18RW Ctle depth When using CTLE fine-grained tuning, determineswhere to set final value in case of a tie. Th

Word Addr Bit R/W Name Description0x4D20RO Link Trained -Receiver statusWhen set to 1, the receiver is trained and is readyto receive data. When set t

Word Addr Bit R/W Name Description0x4D39:0RW ber_time_frames Specifies the number of training frames to examinefor bit errors on the link for each ste

Word Addr Bit R/W Name Description0x4D45:0ROorRWLD coefficientupdate[5:0]Reflects the contents of the first 16-bit word of thetraining frame sent from

Word Addr Bit R/W Name Description0x4D413:8RO LD coefficientstatus[5:0]Status report register for the contents of thesecond, 16-bit word of the traini

Word Addr Bit R/W Name Description0x4D421:16ROorRWLP coefficientupdate[5:0]Reflects the contents of the first 16-bit word of thetraining frame most re

Word Addr Bit R/W Name Description0x4D429:24RO LP coefficientstatus[5:0]Status report register reflects the contents of thesecond, 16-bit word of the

Word Addr Bit R/W Name Description0x4D527:24 R RXEQ CTLE Setting Most recent ctle_rc setting sent to the reconfigbundle during RX equalization.29:28 R

Table 1-4: Package Details for GX and GT Devices with Transceivers and Hard IP Blocks Located on the Leftand Right Side Periphery of the Device• Packa

Word Addr Bit R/W Name Description0x4D64:0RW LT VODMAX ovrd Override value for the VMAXRULE parameter.When enabled, this value substitutes for theVMAX

Word Addr Bit R/W Name Description0x4D6 to0x4FFReserved for 40G KR Left empty for address compatibility with 40GMAC+PHY KR solution.Hard Transceiver P

Table 2-116: PMA RegistersAddress Bit R/W Name Description0x4441 RW reset_tx_digital Writing a 1 asserts the internal TX digital resetsignal. You must

Related Information• fPLL on page 3-13• CMU PLL on page 3-21• ATX PLL on page 3-3• Using the Altera Transceiver PHY Reset Controller on page 4-9• 10GB

Related Information• Arria 10 Transceiver PHY Design Examples• 10-Gbps Ethernet MAC MegaCore Function User Guide.For more information about latency in

Figure 2-56: Top Level Modules of the 1G/10GbE PHY MegaCore FunctionThe Enhanced PCS receives and transmits XGMII data. The Standard PCS receives and

Item DescriptionRelease Date May 2015Ordering CodesIP-1G10GBASER (primary)IPR-1G10GBASER (renewal code)Product ID 0107Vendor ID 6AF71G/10GbE PHY Perfo

Figure 2-57: 1G/10GbE PHY Block DiagramSequencer(Auto-SpeedDetect)RegistersBlockReconfigurationGigEPCS1588FIFOAuto-NegotiationClause 73Link TrainingCl

information in the MAC as part of the Precision Time Protocol implementation, refer to the 10-GbpsEthernet MAC MegaCore Function User Guide.Reconfigur

You can use a fPLL or a CMU PLL to generate the clock for the TX PMA for the 1G data rate. For the 10Gdata rate, you can use the ATX PLL or the CMU PL

ContentsArria 10 Transceiver PHY Overview ...1-1Device Transceiver Layout...

Figure 1-11: Arria 10 SX Device with 48, 36, and 24 Transceiver Channels and Two Hard IP BlocksTransceiverBankTransceiverBankTransceiverBankTransceive

Signal Name Direction Descriptionrx_cdr_refclk_1g Input The RX 1G PLL reference clock to drive the RXHSSI circuits. Connected to the rx_cdr_refclk[1]i

Signal Name Direction Descriptionrx_div_clk Output This is the receive div33 clock, which is recoveredfrom the received data. It drives the Auto Negot

Related Information• General Options on page 2-129• 10GBASE-R Parameters on page 2-130• 10M/100M/1Gb Ethernet Parameters on page 2-173• Speed Detectio

Parameter Name Options DescriptionEnable tx_clkout port OnOffWhen you turn on this parameter, the tx_clkout port is enabled. Refer to the clock andres

Parameter Name Options DescriptionEnable additional control andstatus pinsOnOffWhen you turn on this parameter, the coreincludes the rx_block_lock and

Table 2-124: Speed DetectionParameter Name Options DescriptionEnable automatic speed detection OnOffWhen you turn this option On, the core includesthe

1G/10GbE PHY InterfacesFigure 2-60: 1G/10GbE PHY Top-Level Signalsxgmii_tx_dc[71:0]xgmii_tx_clkxgmii_rx_dc[71:0]xgmii_rx_clkgmii_tx_d[7:0]gmii_rx_d[7:

Clock and Reset InterfacesTable 2-125: Clock and Reset SignalsSignal Name Direction Descriptiontx_serial_clk_10g Input High speed clock from the 10G P

Signal Name Direction Descriptionrx_analogreset Input Resets the analog RX portion of the transceiverPHY. Synchronous to mgmt_clk.rx_digitalreset Inpu

Signal Name Direction Clock Domain Descriptionxgmii_rx_clkInputClock signalClock for SDR XGMII RX interface to the MAC. Thisclock can be connected to

Figure 1-12: Arria 10 SX Device with 12 Transceiver Channels and One Hard IP BlockTransceiverBankTransceiverBankTransceiverBankTransceiverBankPCIeGen1

Signal Name XGMII Signal Name Descriptionxgmii_rx_dc[8] xgmii_sdr_ctrl[0] Lane 0 controlxgmii_rx_dc[16:9] xgmii_sdr_data[15:8] Lane 1 dataxgmii_rx_dc[

Signal Name Direction Descriptionled_char_err Output 10-bit character error. Asserted for one rx_clkout_1g cycle when an erroneous 10-bitcharacter is

Signal Name Direction Clock Domain Descriptionrx_block_lock Output Synchronous to rx_clkoutAsserted to indicate that the block synchronizerhas establi

Signal Name Direction Clock Domain Descriptionmode_1g_10gbarInput Synchronous to mgmt_clkThis signal selects either the 1G or 10G tx-parallel-data goi

Note: Do not write to any register that is not specified.UG-011432015.05.11Register Definitions2-183Implementing Protocols in Arria 10 TransceiversAlt

Table 2-134: 1G/10GbE Register DefinitionsWordAddrBit R/W Name Description0x4B00RW Reset SEQ When set to 1, resets the 10GBASE-KR sequencer (autorate

WordAddrBit R/W Name Description0x4B10R SEQ Link Ready When asserted, the sequencer indicates the link is ready.1 R SEQ AN timeout When asserted, the

WordAddrBit R/W Name Description0x4C00RW AN enable When set to 1, enables the AN function. The defaultvalue is 1. For additional information, refer to

WordAddrBit R/W Name Description0x4C21RO AN page received When set to 1, a page has been received. When 0, a pagehas not been received. The current va

WordAddrBit R/W Name Description0x4C315:0RW User base page low The AN TX state machine uses these bits if the AN basepages ctrl bit is set. The follow

Related Information• Arria 10 Avalon-ST Interface for PCIe Datasheet• Arria 10 Avalon-MM Interface for PCIe Datasheet• Arria 10 Avalon-MM DMA Interfac

WordAddrBit R/W Name Description0x4C515:0 RW User Next page low The AN TX state machine uses these bits if the AN nextpages ctrl bit is set. The follo

WordAddrBit R/W Name Description0x4CB24:0RO AN LP ADV Tech_A[24:0]Received technology ability field bits of Clause 73 Auto-Negotiation. The 10GBASE-KR

WordAddrBit R/W Name Description0x4D00RW Link TrainingenableWhen 1, enables the 10GBASE-KR start-up protocol.When 0, disables the 10GBASE-KR start-up

WordAddrBit R/W Name Description0x4D014:12RW equal_cnt [2:0]Adds hysteresis to the error count to avoid localminimums. The following values are define

WordAddrBit R/W Name Description0x4D10 RW Restart LinktrainingWhen set to 1, resets the 10GBASE-KR start-up protocol.When set to 0, continues normal o

WordAddrBit R/W Name Description0x4D20RO Link Trained -Receiver statusWhen set to 1, the receiver is trained and is ready toreceive data. When set to

WordAddrBit R/W Name Description0x4D39:0RW ber_time_frames Specifies the number of training frames to examine forbit errors on the link for each step

WordAddrBit R/W Name Description0x4D45:0RO orRWLD coefficientupdate[5:0]Reflects the contents of the first 16-bit word of thetraining frame sent from

WordAddrBit R/W Name Description0x4D414RO Link Training ready- LD Receiver readyWhen set to 1, the local device receiver has determinedthat training i

WordAddrBit R/W Name Description0x4D423RO orRWLP PresetCoefficientsWhen set to 1, the local device TX coefficients are set to astate where equalizatio

Each transceiver bank includes six transceiver channels in all devices except for the devices with 66transceiver channels. These devices (with 66 tran

WordAddrBit R/W Name Description0x4D527:24 R RXEQ CTLE Setting Most recent ctle_rc setting sent to the reconfig bundleduring RX equalization.29:28 R R

WordAddrBit R/W Name Description0x4D64:0RW LT VODMAX ovrd Override value for the VMAXRULE parameter. Whenenabled, this value substitutes for the VMAXR

WordAddrBit R/W Name Description0x4D6to0x4FFReserved for 40G KR Left empty for address compatibility with 40G MAC+PHY KR solution.Related InformationR

Addr Bit Access Name Description0x4821 RO HI_BER High BER status. When set to 1, the PCS reportsa high BER. When set to 0, the PCS does notreport a hi

Addr Bit R/W Name Description0x494(1000BASE-Xmode)5RW FD Full-duplex mode enable for the local device.Set to 1 for full-duplex support.6 RW HD Half-du

Addr Bit R/W Name Description0x495(1000BASE-Xmode)5R FD Full-duplex mode enable for the link partner.This bit must be 1 because only full duplex issup

Addr Bit R/W Name Description0x494(SGMIImode)11:10RW Speed[1:0]Local device speed:• 00: copper interface speed is 10 Mbps• 01: copper interface speed

Addr Bit R/W Name Description0x4960 R LINK_PARTNER_AUTO_NEGOTIATION_ABLESet to 1, indicates that the link partnersupports AN. The default value is 0.1

Addr Bit R/W Name Description0x4A80 RW tx_invpolarity When set, the TX interface inverts the polarityof the TX data to the 8B/10B encoder.1 RW rx_invp

Address Bit R/W Name Description0x466 0 RO pma_rx_is_lockedtodataWhen asserted, indicates that the RX CDR PLL islocked to the RX data, and that the RX

Figure 1-15: Six-Channel GX Transceiver Bank ArchitecturePMAChannel PLL(CDR Only)PCSLocal CGB5CH5PMAChannel PLL(CMU/CDR)PCSLocal CGB4CH4PMAChannel PLL

• ATX PLL on page 3-3• Using the Altera Transceiver PHY Reset Controller on page 4-9• 1G/10GbE PHY Functional Description on page 2-165Design Guidelin

default configuration includes two channels for backplane Ethernet and two channels for line-side (1G/10G) applications.Figure 2-62: 1G/10GbE PHY Only

• ModelSim Verilog• ModelSim VHDL• VCS Verilog• VCS VHDL• NCSIM Verilog• NCSIM VHDL simulationWhen you generate a 1G/10GbE or 10GBASE-KR PHY IP core,

Figure 2-63: XAUI and XGMII LayersOSIReferenceModel LayersApplicationPresentationSessionTransportNetworkData LinkPhysicalPMAPMDMedium10 GbpsOptionalXG

Figure 2-64: XAUI PHY IP CoreXAUI PHY IP Core4 x 3.125 Gbps serialXAUI PHY IPHard PMAPCS8B/10BWord AlignerPhase CompSDR XGMII72 bits @ 156.25 MbpsAva

Figure 2-65: Transceiver Channel Datapath for XAUI ConfigurationThe XAUI configuration uses both the soft PCS and the Standard PCS as shown in the fol

Figure 2-66: Implementation of the XGMII Specification in Arria 10 Devices ConfigurationLane 0Interface Clock (156.25 MHz)8-bitInterface Clock (156.25

The transmitter state machine performs the following functions in conformance with the 10GBASE-XPCS:• Encoding the XGMII data to PCS code groups• Conv

XAUI PHY Device Family SupportIP cores provide either final or preliminary support for target Altera device families. These terms have thefollowing de

Note: When configuring ATX PLL, the PMA width setting must be set to 20-bit per transceiver channel.This ensures that the serial clock is running at 3

Figure 1-16: GT Transceiver Bank ArchitectureIn GT devices, the transceiver banks GXBL1E, GXBL1F, GXBL1G, and GXBL1H include GT channels.CH1PMAChannel

1. For Which device family will you be using?, select Arria 10.2. Click Installed IP > Library > Interface Protocols > Ethernet > XAUI PHY

Name Value DescriptionEnable dynamic reconfiguration On / Off When you turn this option on, you can connectthe dynamic reconfiguration ports to an ext

Figure 2-70: Interleaved SDR XGMII Data MappingInterleaved ResultOriginal XGMII Data[63:56][55:48][47:40][39:32][31:24][23:16][15:8][7:0][63:56] [31:2

Signal Name Direction Descriptionxgmii_rx_inclk Input The XGMII SDR RX input clock which runs at 156.25MHz. This port is only available when Enable ph

Signal Name Direction Descriptionrx_ready Output Indicates PMA RX has exited the reset state and thetransceiver can receive data. Synchronous to mgmt_

XAUI PHY Register Interface and Register DescriptionsThe Avalon-MM PHY management interface provides access to the XAUI PHY IP core PCS, PMA, andtrans

Word Addr Bits R/W Register Name Description0x042 [1:0]W reset_control(write) Writing a 1 to bit 0 initiates a TX digitalreset using the reset control

Word Addr Bits R/W Register Name Description0x066 [31:0] RO pma_rx_is_lockedtodata When asserted, indicates that the RX CDRPLL is locked to the RX dat

Related InformationAvalon Interface SpecificationsXAUI PHY TimeQuest SDC ConstraintRefer to the "Timing Constraints for Bonded PCS and PMA Channe

PCI Express (PIPE)You can use Arria 10 transceivers to implement a complete PCI Express solution for Gen1, Gen2, andGen3, at data rates of 2.5, 5.0, a

Related Information• PLLs and Clock Networks on page 3-1• Transceiver BasicsOnline training course for transceivers.PHY Layer Transceiver ComponentsTr

Transceiver Channel Datapath for PIPEFigure 2-72: Transceiver Channel Datapath for PIPE Gen1/Gen2 ConfigurationsPIPE InterfaceRX FIFOByteDeserializer8

Table 2-154: Supported Features for PIPE ConfigurationsProtocol FeatureGen1(2.5 Gbps)Gen2(5 Gbps)Gen3(8 Gbps)x1, x2, x4, x8 link configurations Yes Ye

configuration is based on the PIPE 2.0 specification. If you use a PIPE configuration, you must implementthe PHY-MAC layer using soft IP in the FPGA f

Receiver DetectionThe PIPE interface block in Arria 10 transceivers provides an input signal pipe_tx_detectrx_loopbackfor the receiver detect operatio

Figure 2-74: Rate Match DeletionThis figure shows an example of rate match deletion in the case where two /K28.0/ SKP symbols must bedeleted. Only one

Figure 2-77: Rate Match FIFO EmptyThe rate match FIFO automatically inserts /K30.7/ (9'h1FE) after the data byte that causes the FIFO tobecome em

Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express 2.0Gen3 FeaturesThe following subsections describes the Arria 10 transceiver b

PCIe Gen3 CapabilityMode EnabledGen1 Gen2 Gen3pipe_rate [1:0] 2'b00 2'b01 2'b1xFigure 2-79: Rate Switch ChangeThe block-level diagram b

Figure 2-80: Speed Change Sequencepipe_tx_elecidlepipe_rate[1:0]pipe_sw[1:0]pipe_sw_done[1:0]pipe_phy_status00 1000001010Gen3 Transmitter Electrical I

CDR ControlThe CDR control block performs the following functions:• Controls the PMA CDR to obtain bit and symbol alignment• Controls the PMA CDR to d

Table 1-6: PCS Types Supported by GX Transceiver ChannelsPCS Type Data RateStandard PCS 611 Mbps to 12 GbpsEnhanced PCS 960 Mbps (12) to 17.4 GbpsPCIe

How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 ModesFigure 2-83: Use ATX PLL or fPLL for Gen1/Gen2 x1 ModeCDRCGBCh 4CDRCGBCh 3CDRCGBCh 2CDRCGBCh

Figure 2-84: Use ATX PLL or fPLL for Gen1/Gen2 x4 ModeCDRCGBCh 4CDRCGBCh 3CDRCGBCh 2CDRCGBCh 1CDRCGBCh 0CDRCGBCh 5X6Network666 666MasterCGBMasterCGBXN

Figure 2-85: Use ATX PLL or fPLL for Gen1/Gen2 x8 ModeCDRCGBCh 4CDRCGBCh 3CDRCGBCh 2CDRCGBCh 1CDRCGBCh 0CDRCGBCh 56666MasterCGB66MasterCGBATX PLL1fPLL

Figure 2-86: Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x1 ModeCDRCGBCh 4CDRCGBCh 3CDRCGBCh 2CDRCGBCh 1CDRCGBCh 0CDRCGBCh 544MasterCGB1MasterCGB0666666X1

Figure 2-87: Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x4 ModeCDRCGBCh 4CDRCGBCh 3CDRCGBCh 2CDRCGBCh 1CDRCGBCh 0CDRCGBCh 5X6Network666 666MasterCGBMaster

Figure 2-88: Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x8 ModeCDRCGBCh 4CDRCGBCh 3CDRCGBCh 2CDRCGBCh 1CDRCGBCh 0CDRCGBCh 56666MasterCGB66MasterCGBATX PLL

How to Implement PCI Express (PIPE) in Arria 10 TransceiversBefore you beginYou must be familiar with the Standard PCS architecture, Gen3 PCS architec

Figure 2-89: Connection Guidelines for a PIPE Gen3 DesignATX PLLand MasterCGB (Gen3)fPLL(Gen1/Gen2)Arria 10 Transceiver Native PHYtx_bonding_clockstx_

Gen1 PIPE Gen2 PIPE Gen3 PIPETransceiver mode TX / RX Duplex TX / RX Duplex TX / RX DuplexNumber of data channelsGen1 x1: 1 channelGen1 x2: 2 channels

Gen1 PIPE Gen2 PIPE Gen3 PIPEInitial TX PLL clock input selection0 0Gen1 / Gen2 clockconnection should be usedfor Initial clock inputselection in Gen3

Figure 1-18: GT Transceiver Channel in Full Duplex Mode Operating Between 17.4 Gbps and 28.3 GbpsNotes:(3) The Standard PCS and PCIe Gen3 PCS blocks a

Gen1 PIPE Gen2 PIPE Gen3 PIPEEnable rx_pma_qpipulldnport (QPI)Off Off OffEnable rx_is_lockedtodataportOptional Optional OptionalEnable rx_is_lockedtor

Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPEEnable TX 8B/10B encoder Enabled Enabled EnabledEnable TX 8B/10B disparitycontrolEnabled Enabled EnabledEnable

Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPEEnable TX bit reversal Off Off OffEnable TX byte reversal Off Off OffEnable TX polarity inversion Off Off OffEn

Signal Name Gen1 (TX ByteSerializer andRX ByteDeserializerdisabled)Gen1 (TX ByteSerializer and RXByte Deserializerin X2 mode), Gen2(TX Byte Serializer

Signal Name Gen1 (TX ByteSerializer andRX ByteDeserializerdisabled)Gen1 (TX ByteSerializer and RXByte Deserializerin X2 mode), Gen2(TX Byte Serializer

Native PHY IP Ports for PIPEFigure 2-90: Signals and Ports of Native PHY IP for PIPE-reconfig_resetreconfig_clkreconfig_avmmtx_digitalresettx_dataktx_

Port Direction Clock Domain Descriptiontx_serial_clk0 / tx_serial_clk1In N/AThe high speed serial clock generatedby the PLL.Note: For Gen3 x1 ONLY tx_

Port Direction Clock Domain Descriptionpipe_tx_sync_hdr[1:0] In tx_coreclkinFor Gen3, indicates whether the 130-bit block transmitted is a Data orCont

Port Direction Clock Domain Descriptionpipe_tx_compliance In tx_coreclkinAsserted for one cycle to set therunning disparity to negative. Usedwhen tran

Port Direction Clock Domain Descriptionpipe_tx_deemph In AsynchronousTransmit de-emphasis selection. InPCI Express Gen2 (5 Gbps) mode itselects the tr

Note: 1. The GT channels can also operate in PCS Direct configuration for data rates from 611 Mbps to28.3 Gbps. The PCS Direct datapath that bypasses

Port Direction Clock Domain Descriptionpipe_rate[1:0] In AsynchronousThe 2-bit encodings defined in thefollowing list:2'b00: Gen1 rate (2.5 Gbps)

Port Direction Clock Domain Descriptionpipe_rx_sync_hdr[1:0] Out rx_coreclkinFor Gen3, indicates whether the 130-bit block being transmitted is a Data

Port Direction Clock Domain Descriptionpipe_rx_status[2:0] Out rx_coreclkinSignal encodes receive status and errorcodes for the receive data stream an

Note: Whichever channel you pick as the PCS master, the fitter will select physical CH1 or CH4 of atransceiver bank as the master channel. This is bec

Figure 2-92: x4 ConfigurationThe figure below shows an alternate way of placing 4 bonded channels. In this case, the logical PCSMaster Channel number

Figure 2-93: x8 ConfigurationFor x8 configurations, Altera recommends you choose a master channel that is a maximum of fourchannels away from the fart

Figure 2-94: x4 Alternate ConfigurationThe figure below shows an alternate way of placing 4 bonded channels. In this case, the logical PCSMaster Chann

Phase 0Phase 0 includes the following steps:1. The upstream component enters Phase 0 of equalization during Recovery.Rcvrconfig by sending EQTS2 train

Where: C0 is the main cursor (boost), C-1 is the pre-cursor (pre-shoot), and C+1 is the post-cursor (de-emphasis).3. This process is repeated until th

CPRIThe common public radio interface (CPRI) is a high-speed serial interface developed for wireless networkradio equipment controller (REC) to uplink

IP Core File Locations...2-75Interlake

Channel PLL (CMU/CDR PLL)A channel PLL resides locally within each transceiver channel. Its primary function is clock and datarecovery in the transcei

Table 2-164: Channel Width Options for Supported Serial Data RatesSerial Data Rate(Mbps)Channel Width (FPGA-PCS Fabric)8/10 Bit Width 16/20 Bit Width8

Data Rate (Mbps) Base Data Rate Local CGB Divider3072.0 6144.0 24915.2 9830.4 26144.0 6144.0 19830.4 9830.4 1Supported Features for CPRIThe CPRI proto

Figure 2-97: Word Aligner in Deterministic Mode Waveformrx_clkoutrx_std_wa_patternalignrx_parallel_datarx_errdetectrx_disperrrx_patterndetectrx_syncst

Table 2-167: Word Aligner Signal Status Behaviors in Manual ModePCS-PMA Interface Width rx_std_wa_patternalignBehaviorrx_syncstatusBehaviorrx_patternd

Refer to Select and Instantiate the PHY IP Core on page 2-2 for more details.2. Select CPRI (Auto) or CPRI (Manual) from the Transceiver configuration

Figure 2-100: Connection Guidelines for a CPRI PHY DesignPLL IPDataGeneratorDataVerifierArria 10 Transceiver Native PHYReset Controllerpll_powerdownrx

Native PHY IP Parameter Settings for CPRITable 2-168: General and Datapath OptionsThe first two sections of the Parameter Editor for the Native PHY IP

Parameter Valuetx_pma_div_clkout division factor 2Enable tx_pma_elecidle port OffEnable tx_pma_qpipullup port (QPI) OffEnable tx_pma_qpipulldn port (Q

Parameters ValueFPGA fabric / Standard TX PCS interface width 32FPGA fabric / Standard RX PCS interface width 32Enable 'Standard PCS' low la

Parameters ValueNumber of word alignment patterns to achievesync3 (38)Number of invalid data words to lose sync 3 (39)Number of valid data words to de

Related Information• Calibration on page 7-1• Arria 10 Device Datasheet• Configuration, Design Security, and Remote System Upgrades in Arria 10 Device

Parameter ValueGenerate C header file OffGenerate MIF (Memory Intialization File) OffTable 2-173: Generation OptionsParameter ValueGenerate parameter

Figure 2-101: Transceiver Channel Datapath and Clocking for Basic (Enhanced PCS) ConfigurationTransmitter Enhanced PCSTransmitter PMAReceiver PMARecei

Figure 2-102: Transceiver Channel Datapath and Clocking for a Basic with KR FEC ConfigurationTransmitter Enhanced PCSTransmitter PMAReceiver PMAReceiv

Figure 2-103: Signals and Ports of Native PHY IP for Basic (Enhanced PCS) and Basic with KR FECConfigurationsReconfigurationRegistersNIOSHard Calibrat

Figure 2-104: Connection Guidelines for a Basic (Enhanced PCS) Transceiver DesignReset ControllerArria 10 Transceiver Native PHYDesignTestbench32-bit

Native PHY IP Parameter Settings for Basic (Enhanced PCS) and Basic with KR FECTable 2-174: General and Datapath ParametersThe first two sections of t

Parameter RangeEnable tx_pma_div_clkout port On / Offtx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66Enable tx_pma_elecidle port On / OffE

Table 2-177: Enhanced PCS ParametersParameter RangeEnhanced PCS/PMA interface width 32, 40, 64Note: Basic with KR FEC allows 64 onlyFPGA fabric/Enhanc

Parameter RangeEnable rx_enh_fifo_pfull portOn / OffEnable rx_enh_fifo_empty portOn / OffEnable rx_enh_fifo_pempty portOn / OffEnable rx_enh_fifo_del

Parameter RangeEnable tx_enh_frame portOn / OffEnable rx_enh_frame portOn / OffEnable rx_enh_frame_dian_status portOn / OffTable 2-178: Dynamic Reconf

Implementing Protocols in Arria 10Transceivers22015.05.11UG-01143SubscribeSend FeedbackTransceiver Design IP BlocksFigure 2-1: Arria 10 Transceiver De

Double-width mode: 40:40, 64:64, or 66:643. Select Phase_compensation in the TX and RX FIFO mode list.4. If you need the Scrambler and Descrambler fea

Figure 2-107: RX Bit Sliprx_clkoutrx_bitsliprx_parallel_data[63:0]64’d164’d0RX Polarity InversionUse the RX polarity inversion feature to swap the pos

Figure 2-108: Transceiver Channel Datapath and Clocking for the Basic and Basic with Rate MatchConfigurationsThe clocking calculations in this figure

Figure 2-109: Transceiver Channel Datapath and Clocking for Basic Configuration with Low LatencyEnabledThe clocking calculations in this figure are fo

This mode adds rx_patterndetect and rx_syncstatus. You can select the Enable rx_std_wa_patterna‐lign port option to enable rx_std_wa_patternalign. An

Figure 2-111: Manual Mode when the PCS-PMA Interface Width is 10 Bitstx_parallel_data = 10'h3BC and the word aligner pattern = 0x3BCrx_std_wa_pat

Figure 2-113: Manual Mode when the PCS-PMA Interface Width is 20 Bitstx_parallel_data = 20'hFC3BC and the word aligner pattern = 0x3BCrx_std_wa_p

You can verify this feature by monitoring rx_parallel_data.Figure 2-114: Synchronization State Machine Mode when the PCS-PMA Interface Width is 20 Bit

Figure 2-117: RX Bit Slip in 16-bit Modetx_parallel_data = 16'hfcbc979f cbcf e5e7 f2f3 f979 fcbcfcbcrx_std_bitslipboundaryselrx_bitsliptx_paralle

a bus in which each bit corresponds to a channel. As long as rx_std_bitrev_ena is asserted, the RX datareceived by the core shows bit reversal.You can

Transceiver Design FlowFigure 2-2: Transceiver Design FlowNote: The design examples on the alterawiki page provide useful guidance for developing your

Parameter Value DescriptionRX rate match insert/delete –vepattern (hex)20 bits of dataspecified as a hexadec‐imal stringThe first 10 bits correspond t

Figure 2-123: Rate Match FIFO Insertion with Three Skip Patterns Required for Insertiontx_parallel_datarx_parallel_dataFirst Skip ClusterSecond Skip C

Parameter Value DescriptionRX rate match insert/delete -ve pattern(hex)20 bits of dataspecified as ahexadecimal stringThe first 10 bits correspond to

Figure 2-127: Rate Match FIFO Insertion with Four Skip Patterns Required for InsertionDx.y K28.0 Dx.y K28.5 K28.0 K28.0tx_parallel_data[19:10]rx_paral

The following ports are added:• tx_datak• rx_datak• rx_runningdisp• rx_disperr• rx_errdetectrx_datak and tx_datak indicate whether the parallel data i

6. Ensure that RX rate match FIFO mode is disabled.7. Set the RX word aligner mode to bitslip.8. Set the RX word aligner pattern length to 7 or 16.Not

Figure 2-133: TX Bit Slip in 20-bit Modetx_parallel_data = 20'hF3CBC. tx_std_bitslipboundarysel = 5'b00111 (bit slip by 7 bits).tx_std_bitsl

How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in Arria 10TransceiversBefore you beginYou should be familiar with t

Figure 2-136: Signals and Ports of Native PHY IP for Basic, Basic with Rate Match Configurationsreconfig_resetreconfig_clkreconfig_avmmtx_digital_rese

Figure 2-137: Connection Guidelines for a Basic/Custom DesignresetPatternGeneratorPatternCheckerPLL IPResetControllerArria 10TransceiverNativePHYtx_pa

not have the option to set the speed grade. Specify the device family and speed grade when you create theQuartus II project.You can also instantiate t

Parameter RangeTransceiver configuration rulesBasic/Custom (Standard PCS)Basic/Custom w/Rate Match (StandardPCS)PMA configuration rules basicTransceiv

Parameter RangeEnable tx_pma_txdetectrx port (QPI) On/OffEnable tx_pma_rxfound port (QPI) On/OffEnable rx_seriallpbken port On/OffTable 2-182: RX PMA

Parameter RangeTX FIFO modelow_latencyregister_fifofast_registerRX FIFO Modelow_latencyregister_fifoEnable tx_std_pcfifo_full port On/OffEnable tx_std

Parameter RangeRX word aligner modebitslipmanual (PLD controlled)synchronous state machineRX word aligner pattern length 7, 8, 10, 16, 20, 32, 40RX wo

Table 2-184: Dynamic Reconfiguration ParametersParameter RangeEnable dynamic reconfiguration On/OffShare reconfiguration interface On/OffEnable Altera

Notes on grouping channels Ch0, Ch1, and Ch2:• If channels 0 and 1 are configured as GT channels, channel 2 is unusable.• If either channel 0 or 1 is

Figure 2-138: GT Channel ConfigurationCMU or CDRCGBCh 4CDRCGBCh 3CDRCGBCh 2CGBCh 1CDRCGBCh 0CDRCGBCh 5ATX PLL1ATX PLL0CMU or CDRWhen both the channels

Reset ControllerEach GT channel instantiated will have independent analog and digital reset ports. Refer to the ResettingTransceiver Channels chapter

Parameter RangeInitial TX PLL clock input selection 0, 1, 2, 3Enable tx_pma_clkout port On / OffEnable tx_pma_div_clkout port On / Offtx_pma_div_clkou

Parameter RangeEnable rx_pma_qpipulldn port (QPI) On / OffEnable rx_is_lockedtodata port On / OffEnable rx_is_lockedtoref port On / OffEnable rx_set_l

Figure 2-3: Arria 10 Transceiver PHY TypesRelated InformationArria 10 Transceiver Protocols and PHY IP Support on page 2-10Configure the PHY IP CoreCo

Table 2-193: Generation Options ParametersParameter RangeGenerate parameter documentation fileOn / OffFigure 2-139: Connection Guidelines for an Enhan

as a starting point. Or, you can use the protocol presets described in Presets. You can then modify thesettings to meet your specific requirements.• E

Figure 2-141: ATX PLL IP with GT Clock Lines Enabled6. Create a transceiver reset controller. Refer to Resetting Transceiver Channels on page 4-1 for

5. Instantiate and configure your PLL.6. Create a transceiver reset controller. You can use your own controller or use the Altera TransceiverPHY Reset

You can simulate the following netlist:• The RTL functional netlist—This netlist provides cycle-accurate simulation using Verilog HDL,SystemVerilog, a

The Test Benches dialog box appears.c. Click New.d. Under Create new test bench settings, for Test bench name type the test bench name. For Toplevel m

How to Use NativeLink to Run a ModelSim-Altera RTL SimulationFigure 2-143: NativeLink Simulation Flow DiagramSpecify EDA Simulator &Simulator Dire

of the device. Consequently, you must route any signal that you want to observe to the top-level ofyour design.4. To monitor additional signals, highl

Figure 2-144: Using NativeLink with Third-Party SimulatorsSpecify EDA Simulator &Simulator DirectoryPerform Functional SimulationDebug Design &

Table 2-195: Simulator PathSimulator PathMentor Graphics ModelSimMentor Graphics QuestaSim<drive>:\<simulator install path>\win32(Windows)

Related Information• Using the Arria 10 Transceiver Native PHY IP Core on page 2-17For information on Native PHY IP.• Interlaken on page 2-76• Gigabit

Figure 2-145: Custom flow SimulationStart Simulator & OpenQuartus II ProjectDebug Design &Make RTL ChangesDoes Simulation Give Expected Result

Complete the following steps to compile the simulation model libraries using the Simulation LibraryCompiler:1. On the Tools menu, click Launch Simulat

Simulator Simulation File UseAldec Riviera Pro /simulation/ aldec/rivierapro_setup.tclSource directly with yoursimulator.Synopsys VCS /simulation/syno

This utility compiles IP simulation models into simulation libraries. Complete the following steps to usethis command in Qsys:1. On the Qsys Tools men

PLLs and Clock Networks32015.05.11UG-01143SubscribeSend FeedbackThis chapter describes the transceiver phase locked loops (PLLs), internal clocking ar

Figure 3-1: Arria 10 PLLs and Clock NetworksLocal CGBCDRCH2Local CGBCDR/CMUCH1Local CGBCDRCH0fPLLATXPLLMasterCGBLocal CGBCDRCH5Local CGBCDR/CMUCH4Loca

• Channel Bonding on page 3-44PLLsTable 3-1: Transmit PLLs in Arria 10 DevicesPLL Type Data Rate Range CharacteristicsAdvanced Transmit (ATX) PLL 611

Figure 3-2: ATX PLL Block DiagramVCO 1VCO 2VCO 3LockDetectorPFDCP &LFRefclkMultiplexer22/2M CounterDelta SigmaModulator (1)N CounterL CounterRef

signal at the output of the N counter to the feedback clock (fbclk) signal. The PFD generates an "Up"signal when the reference clock's

1. Open the Quartus II software.2. Click Tools > IP Catalog.3. In IP Catalog, under Library > Transceiver PLL > , select Arria 10 Transceive

To instantiate a PLL IP:1. Open the Quartus II software.2. Click Tools > IP Catalog.3. At the top of the IP Catalog window, select Arria 10 device

Parameter Range DescriptionPrimary PLL clock outputbuffer GX clock outputbufferGT clock outputbufferCascade SourceSpecifies which PLL output is activ

Parameter Range DescriptionPLL integer reference clockfrequencyUser-defined Specifies the reference clock frequency for the ATXPLL in fractional mode.

Parameter Range DescriptionEnable bonding clock outputportsOn/Off Enables the tx_bonding_clocks output ports of themaster CGB used for channel bonding

Parameter Range DescriptionGenerate SystemVerilogpackage file On/Off Generates a SystemVerilog package file containingall relevant parameters used by

Port Direction Clock Domain Descriptionpll_locked Output Asynchronous Active high status signal whichindicates if the PLL is locked.pll_pcie_clk Outpu

Port Direction Clock Domain Descriptionmcgb_rst Input Asynchronous Master CGB reset control.If you use PLL feedbackcompensation bonding mode,deassert

fPLLThe fractional PLL (fPLL) is used for generating lower clock frequencies. It supports both integer andfractional frequency synthesis. The fPLL can

Reference Clock MultiplexerThe refclk mux selects the reference clock to the PLL from the various available reference clock sources.N CounterThe N cou

Dynamic Phase ShiftThe dynamic phase shift block allows you to adjust the phase of the M and C counters in user mode. Infractional mode, dynamic phase

Parameters Range DescriptionEnable fractional mode On/Off Enables the fractional frequency mode.This enables the PLL to output frequencies whichare no

Figure 2-4: Arria 10 Transceiver PLL TypesRelated InformationPLLs on page 3-3Configure the PLL IP CoreUnderstand the available PLLs, clock networks, a

Table 3-8: fPLL—Master Clock Generation Block Parameters and SettingsParameters Range DescriptionInclude Master ClockGeneration BlockOn/Off When enabl

Parameter Range DescriptionEnable Altera Debug MasterEndpointOn/Off When you turn this option ON, the transceiver PLLIP core includes an embedded Alte

Port Range Clock Domain Descriptionpll_refclk0 input N/A Reference clock input port 0.There are five reference clockinput ports. The number ofreferenc

Port Range Clock Domain Descriptionreconfig_readdata0[31:0] output reconfig_clk0 32-bit data bus. Carries theread data from the specifiedaddress.recon

Port Range Clock Domain Descriptionpcie_sw[1:0] input Asynchronous 2-bit rate switch control inputused for PCIe protocolimplementation.pcie_sw_done[1:

Figure 3-4: CMU PLL Block DiagramVCOPFDCP +LFM CounterVCOCalibrationN CounterL CounterLock toReferenceControllerUser Control(LTR/LTD)Lock to Reference

The PFD output is used by the charge pump and loop filter to generate a control voltage for the VCO. Thecharge pump translates the "Up"/&quo

CMU PLL IP CoreTable 3-12: CMU PLL Parameters and SettingsParameters Range DescriptionMessage level for rule violations ErrorWarningSpecifies the mess

Table 3-13: CMU PLL—Dynamic ReconfigurationParameters Range DescriptionEnable dynamic reconfigura‐tionOn/Off Enables the PLL reconfiguration interface

Table 3-15: CMU PLL IP PortsPort Range Clock Domain Descriptionpll_powerdown input Asynchronous Resets the PLL when assertedhigh.pll_refclk0 input N/A

• fPLL IP Core on page 3-15• CMU PLL IP Core on page 3-24• Using PLLs and Clock Networks on page 3-49Generate the PLL IP CoreAfter configuring the PLL

Port Range Clock Domain Descriptionreconfig_address0[9:0] input reconfig_clk0 10-bit address bus used tospecify address to be accessed forboth read an

Altera recommends using the dedicated reference clock pins and the reference clock network for the bestjitter performance.Figure 3-5: Input Reference

Figure 3-6: Dedicated Reference Clock PinsThere are two dedicated reference clock (refclk) pins available in each transceiver bank. The bottomrefclk p

The receiver input pin drives the reference clock network, which can then feed any number of transmitterPLLs on the same side of the device. When a re

x1 Clock LinesThe x1 clock lines route the high speed serial clock output of a PLL to any channel within a transceiverbank. The low speed parallel clo

Figure 3-7: x1 Clock LinesCMU or CDRCGBCh 4CDRCGBCh 3CDRCGBCh 2CGBCh 1CDRCGBCh 0CDRCGBCh 5x1 NetworkMasterCGBMasterCGBATX PLL1ATX PLL0fPLL1fPLL0CMU or

The x6 clock lines also drive the xN clock lines which route the clocks to the neighboring transceiverbanks.Figure 3-8: x6 Clock LinesCGBCh 4CDRCGBCh

configurations, the low speed parallel clock output of the master CGB is used, and the local CGB withineach channel is bypassed. For non-bonded config

a bonded group must share the same voltage. The data rates supported by different transceiver voltagelevels are pending characterization.Related Infor

Figure 3-10: GT Clock LinesCMU or CDRCGBCh 4CDRCGBCh 3CDRCGBCh 2CGBCh 1CDRCGBCh 0CDRCGBCh 5ATX PLL1ATX PLL0CMU or CDRClock Generation BlockIn Arria 10

Receiver Input Pins...3-29PLL Cas

Connect the PHY IP to the PLL IP and Reset ControllerConnect the PHY IP, PLL IP, and the reset controller. Write the top level module to connect all t

Each transmitter channel has a local clock generation block (CGB). For non-bonded channel configura‐tions, the serial clock generated by the transmit

Figure 3-11: Clock Generation Block and Clock NetworkThe local clock for each transceiver channel can be sourced from either the local CGB via the x1

FPGA Fabric-Transceiver Interface ClockingThe FPGA fabric-transceiver interface consists of clock signals from the FPGA fabric into the transceiverand

Figure 3-12: FPGA Fabric - Transceiver Interface ClockingInput Reference ClockRX FIFOByteDeserializer8B/10B DecoderRate Match FIFOReceiver PMAWord Ali

Note: Refer to the "TX PMA Optional Ports" table in PMA Parameters section for details about selectingthe division factor.These clocks can b

If you choose to use a different clock than the tx_clkout to clock the write side of the phase compensa‐tion FIFO, then you must ensure that the clock

For configurations that use the byte deserializer block, the clock divided by 2 or 4 is used by the bytedeserializer and the write side of the RX phas

You can clock the receiver datapath interface using one of the following methods:• Quartus II selected receiver datapath interface clock• User-selecte

PLL Feedback Compensation BondingIn PLL feedback compensation bonding, channels are divided into bonded groups based on physicallocation with a three-

For PMA bonding, either x6/xN or PLL feedback compensation bonding is used. For PCS bonding, someof the PCS control signals within the bonded group ar

Related InformationQuartus II Incremental Compilation for Hierarchical and Team-Based DesignFor more information about compilation details.Verify Desi

Selecting Channel Bonding SchemesIn Arria 10 devices, select PMA and PCS bonding for bonded protocols that are explicitly supported bythe hard PCS blo

Figure 3-18: PLL Feedback and Cascading Clock NetworkPLL Feedback and Cascading Clock NetworkfPLL1fbclkrefclkCATX PLL 1refclkfbclkMMaster CGB1fPLL0ref

For PLL cascading, connections (1) and (3) are used to connect the output of one PLL to the referenceclock input of another PLL. Arria 10 transceivers

Figure 3-19: PHY IP Core and PLL IP Core Connection for Single Channel x1 Non-Bonded ConfigurationExampleTransceiver PLLInstance (5 GHz)PLLNative PHY

Figure 3-20: PHY IP Core and PLL IP Core Connection for Multi-Channel x1 Non-Bonded ConfigurationTransceiver PLLInstance (5 GHz)ATX PLLTransceiver PLL

Implementing Multi-Channel xN Non-Bonded ConfigurationUsing the xN non-bonded configuration reduces the number of PLL resources and the reference cloc

• In this case, the PLL IP core has mcgb_serial_clk output port. This represents the xN clock line.• The Native PHY IP core has 10 (for this example)

Implementing x6/xN Bonding ModeFigure 3-23: PHY IP Core and PLL IP Core Connection for x6/xN Bonding ModeTransceiver PLLInstance (5 GHz)ATX PLLNative

• In this case, the PLL IP core has tx_bonding_clocks output bus with width [5:0].• The Native PHY IP core has tx_bonding_clocks input bus with width

Figure 3-25: PHY IP Core and PLL IP Core Connection for PLL Feedback Compensation BondingTransceiver PLLInstance (5 GHz)ATX PLLNative PHY Instance(10

Protocol Transceiver IP PCS Support TransceiverConfigurationRule(15)Protocol Preset (16)1000BASE-X GigabitEthernetNative PHY IP Standard GbE GIGE - 1.

• If you use the ATX PLL, set the following configuration settings:• Under the Master Clock Generation Block Tab• Enable Include Master Clock Generati

Figure 3-26: PLL Cascadingpll_refclk0 hssi_pll_cascade_clkpll_powerdown pll_lockedpll_refclk0pll_powerdownfPLL or ATX PLL (Cascade Source) fPLL or ATX

Mix and Match ExampleIn the Arria 10 transceiver architecture, the separate Native PHY IP core and the PLL IP core schemeallows great flexibility. It

Use the following data rates and configuration settings for PLL IP cores:• Transceiver PLL Instance 0: ATX PLL with output clock frequency of 6.25 GHz

Native PHY IP InstancesIn this example, four Transceiver Native PHY IP instances and four 10GBASE-KR PHY IP instances areused. Use the following data

Connection Guidelines for PLL and Clock Networks• For 12.5 Gbps Interlaken with a bonded group of 10 channels, connect the tx_bonding_clocks to thetra

Resetting Transceiver Channels42015.05.11UG-01143SubscribeSend FeedbackTo ensure that transceiver channels are ready to transmit and receive data, you

When Is Reset Required?You can reset the transmitter (TX) and receiver (RX) data paths independently or together. Therecommended reset sequence requir

Recommended Reset SequenceFigure 4-2: Transmitter and Receiver Reset SequenceFPGA DevicePower Up/OperationEnsure CalibrationCompletedPLL,TX/RX AnalogR

Figure 4-3: Transmitter Reset Sequence After Power-UpDevice Power Uppll_cal_busytx_cal_busypll_powerdowntx_analogresetpll_lockedtx_digitalreset1123Dev

Protocol Transceiver IP PCS Support TransceiverConfigurationRule(15)Protocol Preset (16)100GBASE-R via CAUI Native PHY IP Enhanced Basic (EnhancedPCS)

Figure 4-4: Transmitter Reset Sequence During Device OperationDevice Power Uppll_cal_busytx_cal_busypll_powerdowntx_analogresetpll_lockedtx_digitalres

Figure 4-5: Receiver Reset Sequence Following Power-UpDevice Power Uprx_cal_busyrx_is_lockedtodatarx_analogresetrx_digitalreset123Device in User Mode4

Clock Data Recovery in Manual Lock ModeUse the clock data recovery (CDR) manual lock mode to override the default CDR automatic lock modedepending on

Figure 4-7: Reset Sequence Timing Diagram for Transceiver when CDR is in Manual Lock Moderx_digitalresetrx_set_locktorefrx_set_locktodatarx_is_lockedt

Transceiver Block pll_powerdown tx_analogreset tx_digitalreset rx_analogreset rx_digitalresetTransmitterStandard PCSYesTransmitterEnhanced PCSYesTrans

Figure 4-8: Altera Transceiver PHY Reset Controller System DiagramTransceiverPHY ResetControllerIP CoreTransceiver PHY InstanceReceiverPCSTransmitterP

Parameterizing the Transceiver PHY Reset Controller IPThis section lists steps to configure the Transceiver PHY Reset Controller IP Core in the IP Cat

Name Range DescriptionEnable TX PLL reset control On /Off When On, the Transceiver PHY ResetController IP core enables the reset control ofthe TX PLL.

Name Range DescriptionRX ChannelEnable RX channel reset control On /Off When On, the Transceiver PHY ResetController enables the control logic andasso

Figure 4-9: Transceiver PHY Reset Controller IP Core Top-Level SignalsGenerating the IP core creates signals and ports based on your parameter setting

Protocol Transceiver IP PCS Support TransceiverConfigurationRule(15)Protocol Preset (16)OTU-4 (100G) viaOTL4.10/OIF SFI-SNative PHY IP Enhanced Basic

Signal Name Direction Clock Domain Descriptionrx_cal_busy[<n> -1:0]Input Asynchronous This is calibration status signal from theTransceiver PHY

Signal Name Direction Clock Domain Descriptiontx_digital-reset[<n>-1:0]Output Synchronous to theTransceiver PHYReset Controllerinput clock.Digit

Signal Name Direction Clock Domain Descriptionrx_digital-reset[<n> -1:0]Output Synchronous to theTransceiver PHYReset Controllerinput clock.Digi

Configuration Combination ALUTs Logic RegistersFour transceiver channels,shared TX reset, separate RXresetsapproximately 100 approximately 150Using a

Table 4-7: User-coded Reset Controller, Transceiver PHY, and TX PLL SignalsSignal Name Direction Descriptionpll_powerdownOutput Resets the TX PLL when

Figure 4-11: Combining Multiple PHY Status SignalsANDtx_cal_busy signalsfrom channelsTo reset controllertx_cal_busy input portORNote: This configurati

Figure 4-13: Physical Routing Delay Skew in Bonded ChannelsPHY ResetControllerTXChannel[ n - 1]TXChannel[1]TXChannel[0]Bonded TXChannelstx_digitalrese

For more information about the set_max_skew constraint, refer to the SDC and TimeQuest API ReferenceManual.Related InformationSDC and TimeQuest API Re

Arria 10 Transceiver PHY Architecture52015.05.11UG-01143SubscribeSend FeedbackArria 10 PMA ArchitectureThe Physical Medium Attachment (PMA) acts as th

Figure 5-2: Serializer BlockThe serializer block sends out the least significant bit (LSB) of the input data first.DnD2D1D0ParallelDataSerializerDnD2D

Protocol Transceiver IP PCS Support TransceiverConfigurationRule(15)Protocol Preset (16)SONET STS-96 (5G) viaOIF SFI-5.1sNative PHY IP Enhanced Basic/

Figure 5-3: Transmitter BufferTXVCMTo Serial DataOutput Pins(tx_serial_data)ProgrammablePre-Emphasisand VODReceiverDetectOn-ChipTermination85Ω, 100Ω,

Programmable Pre-EmphasisPre-emphasis can maximize the eye at the far-end receiver. The programmable pre-emphasis module ineach transmit buffer amplif

Figure 5-5: Receiver PMA Block DiagramFPGAFabricReceiverPCSDeserializerParallelDataParallelDataSerialDataSerial ClockReceiver PMACDRSerialDataReceiver

Note: On-chip biasing circuitry is available only if you select OCT. If you select external termination, youmust implement off-chip biasing circuitry

Figure 5-7: CTLE DC and AC Gain ConceptualizationDC GainControlGain(dB)FrequencyGain(dB)FrequencyAC GainControlNote: Final equalization curves will be

When CTLE adaptation is disabled (manual mode), you can select CTLE mode and set CTLE gainthrough the Quartus Assignment Editor /.qsf and the Avalon-M

Supported modes for VGA:• Manual Mode:• In this mode, manual VGA values can be set in Assignment Editor/.qsf or using Avalon MMinterface.• Triggered A

Figure 5-9: Signal ISIISI+ISI-Precursor Cursor PostcursorNotes:• An ideal pulse response is a single data point at the cursor.• Real world pulse respo

Figure 5-10: Channel Pulse ResponseVt1UIRegion of Influencefor Fixed TapsSignal at theChannel InputSignal at theChannel OutputNote: The pulse at the o

How to Enable CTLE and DFETable 5-2: Summary of Receiver Equalization ModesReceiver Equalization ModesCTLE adaptation mode Triggered, ManualDFE adapta

Protocol Transceiver IP PCS Support TransceiverConfigurationRule(15)Protocol Preset (16)8G/4G/2G/1G FibreChannelNative PHY IP Standard Basic/Custom(St

a. For CTLE and DFE in Manual mode, set the CTLE gain value or DFE Taps using the reconfigura‐tion interface. The values are written dynamically and d

Figure 5-12: CDR Sample and ODI Sample to Calculate Bit Error Ratio64 StepsCDRSampleHorizontalOffsetVerticalOffsetODI Sample128 StepsClock Data Recove

signal is asserted active high to indicate that the CDR has locked to the phase and frequency of thereceiver input reference clock.Note: The phase det

rx_set_locktoref rx_set_locktodata CDR Lock Mode1 0 Manual-RX CDR LTRX 1 Manual-RX CDR LTDDeserializerThe deserializer block clocks in serial input da

Figure 5-15: Serial Loopback PathThe serial loopback path sets the CDR to recover the data from serializer while data from receiver serialinput pin is

Figure 5-17: Reverse Loopback Path/Post CDRThe reverse loopback path sets the transmitter buffer to transmit data fed directly from the CDRrecovered d

Figure 5-18: Enhanced PCS Datapath DiagramTransmitter Enhanced PCSTransmitter PMAReceiver PMAReceiver Enhanced PCSTXGearboxtx_serial_dataSerializerInt

The TX FIFO supports the following operating modes:• Phase Compensation mode• Register mode• Interlaken mode• Basic modeRelated InformationReconfigura

Interlaken ModeIn Interlaken mode, the TX FIFO operates as an elastic buffer. In this mode, there are additional signals tocontrol the data flow into

The CRC-32 calculation covers most of the metaframe, including the diagnostic word, except thefollowing:• Bits [66:64] of each word• 58-bit scrambler

Protocol Transceiver IP PCS Support TransceiverConfigurationRule(15)Protocol Preset (16)SATA 3.0/2.0/1.0 and SAS2.0/1.1/1.0Native PHY IP Standard Basi

Figure 5-21: Example Data Pattern for 64B/66B EncodingC0C1C2C3C4C5C6C710PCSTXC<0:3> TXD<0:31> XGMIIDataXGMIIdata66-bitencodeddata1e 0000

PCS-PMA width only. The PRBS generator patterns can only be used when PCS-PMA interface width isconfigured to 10 bits or 64 bits.Table 5-4: Supported

Figure 5-23: Generator for Square Wave Patternn 0sn 1sn is a programmable number of consecutive serial bit 1s and 0s. n is 1, 4, or 8 (n defaults to 4

Figure 5-24: Asynchronous Scrambler in Serial ImplementationS0 S1 S38 S39 S56OUTINS2 S57In synchronous mode, the scrambler is initially reset to diffe

Table 5-5: Inversion Bit DefinitionBit 66 Interpretation0 Bits [63:0] are not inverted; the receiver processes this word without modification1 Bits [6

KR FEC BlocksThe KR FEC blocks in the Enhanced PCS are designed in accordance with the 10G-KRFEC and 40G-KRFEC of the IEEE 802.3 specification. The KR

KR FEC TX GearboxThe KR FEC TX gearbox converts 65-bit input words to 64-bit output words to interface the KR FECencoder with the PMA. This gearbox is

DescramblerThe descrambler block descrambles received data to regenerate unscrambled data using the x58 + x39 +1polynomial. Like the scrambler, it ope

PRBS Pattern 10 bit PCS-PMA width 64 bit PCS-PMA widthPRBS15: x15 + x14 + 1 YesPRBS23: x23 + x18 + 1 YesPRBS31: x31 + x28 + 1 YesFigure 5-30: PRBS9 Ve

Figure 5-31: PRP VerifierErrorCounterTest PatternDetectPseudo RandomVerifiererror_countDescramblerRefer to the Reconfiguration Interface and Dynamic R

Using the Arria 10 Transceiver Native PHY IP CoreThis section describes the use of the Altera-provided Arria 10 Transceiver Native PHY IP core. This I

The RX FIFO supports the following modes:• Phase Compensation mode• Register mode• Interlaken mode (deskew FIFO)• 10GBASE-R mode (clock compensation F

Figure 5-32: RX FIFO as Interlaken Deskew FIFOUserDeskewFSMFPGA Fabric Interfacerx_enh_fifo_align_clrrx_enh_fifo_rd_enrx_enh_fifo_pemptyrx_enh_fifo_pf

Figure 5-33: IDLE Word DeletionThis figure shows the deletion of IDLE words from the receiver data stream.00000000000004ADh 00000000000004AEh070707070

Figure 5-35: IDLE Word InsertionThis figure shows the insertion of IDLE words in the receiver data stream.Idle InsertedBefore InsertionAfter Insertion

Arria 10 Standard PCS ArchitectureThe standard PCS can operate at a data rate up to 12 Gbps. Protocols such as PCI-Express, CPRI 4.2+,GigE, IEEE 1588

Figure 5-37: TX FIFO Block DiagramTXFIFODatapath from FPGA Fabricor PIPE Interfacetx_coreclkintx_clkoutDatapath to Byte Serializer,8B/10B Encoder,or S

Figure 5-38: Byte Serializer Block DiagramByteSerializerdataout(to the 8B/10 Encoderor the TX Bit Slip)datain (from the TX FIFO)/2,/4tx_clkoutRelated

In serialize x4 mode, the byte serializer serializes 32-bit data into 8-bit data. As the parallel data widthfrom the TX FIFO is divided four times, th

8B/10B Encoder Control Code EncodingFigure 5-40: Control Code Encoding Diagramtx_clkout8378 BCBC 0F00 BF3C0 1 0D3.4 D24.3 D28.5 K28.5 D15.0 D0.0 D31.5

8B/10B Encoder Bit Reversal FeatureThe bit reversal feature reverses the order of the bits of the input data. Bit reversal is performed at theoutput o

Figure 2-5: Transceiver Native PHY IP Core Ports and Functional BlocksReconfiguration RegistersEnhanced PCSTransmit and Receive ClocksStandard PCS

Depending on your PCS-PMA interface width, the word aligner can be configured in one of the followingmodes:• Bit slip• Manual alignment• Synchronous s

a new word boundary. If rx_std_wa_patternalign is deasserted, the word aligner maintains the currentword boundary even when it sees the word alignment

PCS-PMA Interface Width Protocol Implementations20• CPRI• Basic• Basic rate matchWord Aligner Pattern Length for Various Word Aligner ModesTable 5-11:

PCS-PMAInterfaceWidthSupported WordAligner ModesSupportedWordAlignerPatternLengthsrx_std_wa_patternalignbehaviorrx_syncstatusbehaviorrx_patterndetectb

PCS-PMAInterfaceWidthSupported WordAligner ModesSupportedWordAlignerPatternLengthsrx_std_wa_patternalignbehaviorrx_syncstatusbehaviorrx_patterndetectb

PCS-PMAInterfaceWidthSupported WordAligner ModesSupportedWordAlignerPatternLengthsrx_std_wa_patternalignbehaviorrx_syncstatusbehaviorrx_patterndetectb

from the PMA is a 10-bit data width, the bit reversal feature switches bit [0] with bit [9], bit [1] with bit[8], and so on. For example, if the 10-bi

• Rate Match FIFO Basic (Double Width) Mode on page 2-300For more information about implementing rate match FIFO in basic double width mode.• How to I

8B/10B Decoder Control Code EncodingFigure 5-43: 8B/10B Decoder in Control Code Group Detectiondatain[9:0]dataout[7:0]D31.5D3.4 D24.3 D28.5 K28.5 D15.

Byte DeserializerThe byte deserializer allows the transceiver to operate at data rates higher than those supported by theFPGA fabric. It deserializes

Transmitter Datapath...5-19Receiver D

Related Information• Configure the PHY IP Core on page 2-4• Interlaken on page 2-76• Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 on page 2-97• 10G

Bonded Byte DeserializerThe bonded byte deserializer is also available for channel-bundled applications such as PIPE. In thisconfiguration, the contro

This section will focus on the basic blocks of PIPE 3.0-based Gen3 PCS architecture. The PIPE 3.0-basedGen3 PCS uses a 128b/130b block encoding/decodi

TX FIFO (Shared with Standard and Enhanced PCS)The TX FIFO in each channel ensures a reliable transfer of data and status signals between the PCSchann

Rate Match FIFOIn asynchronous systems, the upstream transmitter and local receiver can be clocked with independentreference clocks. Frequency differe

Related InformationRate Switch on page 2-235Clock Data Recovery ControlThe CDR control feature is used for the L0s fast exit when operating in PIPE Ge

Reconfiguration Interface and DynamicReconfiguration62015.05.11UG-01143SubscribeSend FeedbackThis chapter explains the purpose and the use of the Arri

master is connected to the Avalon-MM reconfiguration interface. Communication with the channel andPLL reconfiguration interface requires an Avalon-com

Related Information• Interacting with the Reconfiguration Interface on page 6-4• Reconfiguring Channel and PLL Blocks on page 6-3• Configuration Files

Interacting with the Reconfiguration InterfaceEach transmit PLL and channel has a dedicated Avalon-MM slave interface. The transmit PLL instancehas a

Figure 6-3: Reading from the Reconfiguration Interface119XXXXXXXXreconfig_clkreconfig_resetreconfig_addressreconfig_readreconfig_readdatareconfig_wait

• Standard PCS• PCS Direct• Dynamic ReconfigurationTable 2-2: General and Datapath OptionsParameter Value DescriptionMessage level forrule violationse

Figure 6-4: Writing to the Reconfiguration Interface119000000000000000creconfig_clkreconfig_resetreconfig_addressreconfig_readreconfig_readdatareconfi

32'h00000000;localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_VALUE = 1'h0;The SystemVerilog configuration files con

Table 6-3: Transceiver Native PHY or PLL IP Parameters (Base and Modified Configurations)Native PHYInstanceRequired Parameter Settings Saved InBaseCon

Multiple Reconfiguration ProfilesYou can optionally enable multiple configurations or profiles in the same Native PHY IP ParameterEditor for performin

Figure 6-5: Arria 10 Native PHY with Embedded StreamerUser Reconfiguration LogicStreamerADMEODIChannel Configuration RegistersAvalon-MMInterfaceOptio

Table 6-4: Control and Status Register Memory Map for Embedded Reconfiguration StreamerReconfigu‐rationAddress(hex)Reconfigu‐ration BitAttributeNameAt

Steps to Perform Dynamic ReconfigurationYou can dynamically reconfigure blocks in the transceiver channel or PLL through the reconfigurationinterface.

Related Information• Embedded Debug Features on page 6-40• Calibration on page 7-1Direct Reconfiguration FlowUse this flow to perform dynamic reconfig

PMA Analog Feature Address Bit ValuesPre-emphasis 1st pre-tap polarity 0x107 [5]1'b0 = positive1'b1 = negativePre-emphasis 2nd pre-tap 0x108

Changing CTLE Settings in Manual ModeTo change the CTLE settings in manual mode, you can either update the Quartus II Settings File (.qsf)with a known

Parameter Value DescriptionTransceivermodeTX/RX DuplexTX SimplexRX SimplexSpecifies the operational mode of the transceiver.• TX/RX Duplex : Specifies

Serial Loopback ModeIn serial loopback mode, a path exists between the serializer of the transmitter and the CDR of thereceiver, so that the data from

Table 6-8: Bit Values to Be SetAddress Bit Values0x137[7] 1’b10x13C[7] 1’b00x132[5:4] 2’bxx0x142[4] 1’b10x11D[0] 1’b1Reverse Serial Loopback Mode (Pos

Address Bit Values0x13C[7] 1’b00x132[5:4] 2’b000x142[4] 1’b00x11D[0] 1’b0IP Guided Reconfiguration FlowUse the IP guided reconfiguration flow to perfo

Figure 6-10: Timing Diagram for Embedded Streamer Reconfigurationreconfig_clkreconfig_addressreconfig_readreconfig_readdatareconfig_waitrequestreconfi

Table 6-11: Register Map for Switching Transmitter PLLsTransceiver NativePHY PortDescription Address Bitstx_serial_clk0 Represents logical PLL0. Looku

ATX Reference Clock SwitchingYou can use the reconfiguration interface on the ATX PLL instance to specify which reference clocksource drives the ATX P

fPLL Reference Clock SwitchingYou can use the reconfiguration interface on the fPLL instance to specify which reference clock sourcedrives the fPLL. T

Transceiver fPLL Port Description Address Bitspll_refclk2 Represents logical refclk2 for MUX_1. Lookupregister x11F[4:0] stores the mapping fromlogica

Table 6-15: Register Map for Switching CDR Reference Clock InputsNative PHY Port Description Address Bitscdr_refclk0 Represents logical refclk0.Lookup

You can share the reconfiguration interface among all the channels by turning on Share reconfigurationinterface when parameterizing the IP core. When

Transceiver ConfigurationSettingDescriptionBasic/Custom w /RateMatch (Standard PCS)Enforces a standard set of rules including rules for the Rate Match

Port Name Direction Clock Domain Descriptionreconfig_waitrequest Output reconfig_clk A one-bit signal that indicates theAvalon interface is busy. Keep

Port Name Direction Clock Domain Descriptionreconfig_readdata[N*32-1:0] Output reconfig_clk A 32-bit data read bus for each channel.Valid data is plac

Parameter Value DescriptionEnable ODI acceleration logic On / Off Enables soft logic for accelerating bit and erroraccumulation when using ODI.Configu

Parameter Value DescriptionClear all profiles N/A Clears the Native PHY parameter settings for all theprofiles.Refresh selected_profile N/A Equivalent

Figure 6-14: Separate CMU PLL and TX Channel in the Same Physical LocationCMUTX ChannelUser LogicTransceiver PLL IPNative PHY IPLogicalUser LogicNativ

For Native PHY 1—receive-only instance to be merged with Native PHY 0:set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to topdesign:topdesign_inst

Figure 6-15: ODI Block DiagramCTLE DFE CDR DeserializerDeserializerPhaseInterpolatorDeserializerBit ErrorRatioCheckerODIVref Generator ODI SamplerLogi

Address Bits Read /WriteFeature Description0x144 7RW ODI BandwidthSpecify Eye Monitor bandwidth {0x144[7],0x145[7]} according to following encoding:•

Address Bits Read /WriteFeature Description0x168 [7:5] RW ODI Pattern CounterThresholdThe Pattern Counter Threshold specifies howmany patterns ODI wil

Address Bits Read /WriteFeature Description• 7'h7B : Horizontal Phase 13• 7'h7A : Horizontal Phase 14• 7'h79 : Horizontal Phase 15• 7&a

Related Information• Device Transceiver Layout on page 1-3• Enhanced PCS TX and RX Control Ports on page 2-62PMA ParametersYou can specify values for

Address Bits Read /WriteFeature Description• 7'h54 : Horizontal Phase 57• 7'h55 : Horizontal Phase 58• 7'h56 : Horizontal Phase 59• 7&a

Address Bits Read /WriteFeature Description• 7'h26 : Horizontal Phase 101• 7'h27 : Horizontal Phase 102• 7'h24 : Horizontal Phase 103•

Address Bits Read /WriteFeature Description0x14C [5:0] RW Status Selection Select the status signals presented in StatusValue (address 0x177). The fol

a. Set ODI with DFE Enable to 1’b0 to use ODI with DFE disabled. Use ODI with DFE enabled will besupported in futureb. Set Vertical Height to 6’h00 to

e. Set Status Selection in address 0x144 to 6’h2C to select the ODI Pattern Error bits[15:8] in Statusvalue.f. Read Status value in address 0x177 to g

Table 6-23: Capability Registers for the Native PHY IP CoreAddress Type Name Description0x200[7:0] RO IP Identifier Unique identifier for the Native P

The following control and status registers are available for the Native PHY IP core.Table 6-25: Control Registers for the Native PHY IP CoreAddress Ty

Address Type Register Description0x2E2[6] RW override_tx_analogresetSelects whether the receiver listens to theADME tx_analogreset register or the tx_

PRBS Soft AccumulatorsThe Pseudo Random Binary Sequence (PRBS) soft accumulators are used in conjunction with the hardPRBS blocks in the transceiver c

Address Type Name Description0x304[7:0] RO Accumulated error count[31:24]Accumulated error count [31:24]0x305[7:0] RO Accumulated error count[39:32]Ac

Table 2-4: TX Bonding OptionsParameter Value DescriptionTX channelbonding modeNot bondedPMA only bondingPMA and PCSbondingSelects the bonding mode to

ODI acceleration logic is available whether ADME is instantiated separately or as part of the Native PHYIP. To enable ODI acceleration logic with the

Address Type Attribute Name Description0x321[7:0] R ODI Accelerator ErrorCounters[7:0]Only available when you turn on Enable odiacceleration logic in

Linear Feedback Shift Register (LFSR), the next pattern can be determined from the previous pattern.When the PRBS checker receives a portion of the re

Table 6-32: Square Wave Supported Polynomials and Data WidthsPattern Polynomial 64-Bit 10-BitSquare Wave Number of consecutive 1s and 0s: 1, 4, 8 XEna

Reconfigu‐rationAddress(HEX)Reconfigu‐ration BitAttribute Name RelatedAddressesAttributeEncodingBitEncodingDescription0x007 [7:4] prbs_gen_pat 0x8prbs

Reconfigu‐rationAddress(HEX)Reconfigu‐ration BitAttribute Name RelatedAddressesAttributeEncodingBitEncodingDescription0x110 [2:0] ser_modesixty_four_b

Table 6-34: Register Map for PRBS CheckerReconfigura‐tion Address(HEX)Reconfigura‐tion BitAttributeNameRelatedAddressesAttributeEncodingBitEncodingDes

Reconfigura‐tion Address(HEX)Reconfigura‐tion BitAttributeNameRelatedAddressesAttributeEncodingBitEncodingDescription0x13F [3:0] deser_factor10 4&apos

Table 6-35: Register Map for PRBS Pattern InversionReconfigurationAddress (HEX)Reconfigu‐ration BitAttribute Name Bit Encoding Description0x7 [2] tx_s

Reconfigura‐tion Address(HEX)Reconfigura‐tion BitAttribute Name Bit Encoding Description0x74 [7:0] r_tx_seed_a[23:16] Seed A value bit[23:16]0x75 [7:0

Table 2-5: TX PLL OptionsParameter Value DescriptionTX local clockdivision factor1, 2, 4, 8 Specifies the value of the divider available in the transc

(initial profile and target profiles) during timing driven compilation. These timing arcs make the timingmore accurate.When performing a dynamic recon

To enable the Quartus II software to close timing more accurately in this example, the followingconstraints must be created:• create_clock -name tx_cl

Unsupported FeaturesThe following features are not supported by either the Transceiver Native PHY IP or the PLL IPreconfiguration interface:• Reconfig

Calibration72015.05.11UG-01143SubscribeSend FeedbackTransceivers include both analog and digital blocks that require calibration to compensate for pro

To check if the calibration process is on, monitor the pll_cal_busy, tx_cal_busy, and rx_cal_busysignals. The *_cal_busy signals remain asserted as lo

Avalon-MM Interface Arbitration RegistersTable 7-1: Avalon-MM Interface Arbitration RegistersBit Offset Address Description[0] 0x0(51)This bit arbitra

BitPMA Calibration Enable Register OffsetAddress 0x100PMA Calibration Status Register Offset Address0x1017 Reserved ReservedFractional PLL Calibration

Follow these steps to request bus access:1. Read the offset address 0x0.2. Keep the value from MSB [7:2] and replace LSB [1:0] with 0x2.3. Write the n

Figure 7-1: Power-up Calibration Sequence for Non-PCIe Hard IP (HIP) ChannelsFor applications not using PCIe HIP, the power-up calibration starts from

Figure 7-2: Power-up Calibration Sequence for PCIe HIP and non-PCIe ChannelsBank 1Bank 2Bank ...fPLL CalibrationATX PLL CalibrationfPLL CalibrationATX

Parameter Value DescriptionEnable tx_pma_elecidle portOn/Off Enables the tx_pma_elecidle port. When you assert this port,the transmitter is forced int

The proper reset sequence is required after calibration. Altera recommends you use the Altera transceiverreset controller IP which has tx_cal_busy and

Fractional PLL RecalibrationFollow these steps to recalibrate the Fraction PLL (fPLL):1. Request user access to the internal configuration bus by writ

Follow these steps to recalibrate the PMA:1. Request access to the internal configuration bus by writing 0x2 to offset address 0x0[1:0].2. Wait for re

Figure 7-3: Recalibration Sequence when the Transceiver Reference Clock or Data Rate ChangesfPLL CalibrationATX PLL CalibrationRX OffsetCancellation C

The calibration bits for CDR/CMU, TX termination and Vod, and RX Offset Cancellation can be set onetime through the internal configuration bus because

Analog Parameter Settings82015.05.11UG-01143SubscribeSend FeedbackTransceiver analog parameter settings are used to tune the analog functions in the p

Related InformationQuartus II Settings File (.qsf)Describes the commands and options available to modify the assignments in the qsf file.Analog Parame

Analog Parameter Setting Pin Planner or AssignmentEditor NameAssignmentDestinationUsage GuidelineXCVR_A10_RX_ADP_DFE_FXTAP4Receiver Decision FeedbackE

Analog Parameter Setting Pin Planner or AssignmentEditor NameAssignmentDestinationUsage GuidelineXCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1TTransmit

Table 8-4: Available OptionsValue DescriptionSR Chip-to-chip communicationLR Backplane communicationNote: The maximum data rate supported by transceiv

Parameter Value DescriptionPPM detectorthreshold1003005001000Specifies the PPM threshold for the CDR. If the PPM betweenthe incoming serial data and t

Syntaxset_instance_assignment -name XCVR_A10_RX_TERM_SEL <value> -to <rx_serial_data pinname>XCVR_VCCR_VCCT_VOLTAGE - RXPin planner or Ass

Arria 10 transceivers support the following two CTLE modes:• High gain mode• High data rate mode.High gain mode is enabled by default for data rates u

Table 8-7: Available OptionsValue DescriptionRADP_CTLE_ACGAIN_4S_<0 to 28>CTLE AC gain setting <0 to 28>Assign ToRX serial data.Syntaxset_

DescriptionSelects between the RX high gain mode or RX high data rate mode for the equalizer. If no assignment ismade, then NON_S1_MODE is chosen by d

Syntaxset_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL <value> -to <rx_serial_data pinname>Decision Feedback Equalizer (DFE) Settings

Assignment Pin Planner orAssignment EditorNameValue DescriptionXCVR_A10_RX_ADP_DFE_FXTAP5Receiver DecisionFeedback EqualizerFixed Tap FiveCoefficient.

Table 8-12: Available OptionsValue DescriptionSR Chip-to-chip communicationLR Backplane communicationNote: The maximum data rate supported by transcei

Data Rate Value of XCVR_A10_TX_COMPENSATION_ENOthers ENABLE/DISABLEAssign ToTX serial data.Syntaxset_instance_assignment -name XCVR_A10_TX_COMPENSATIO

DescriptionSpecifies the slew rate of the output signal. The valid values span from the slowest rate to the fastest rate.Table 8-15: Available Options

Transmitter Pre-Emphasis SettingsThe programable pre-emphasis block in the transmit buffer amplifies the high frequencies in the transmitdata to compe

Parameters Value DescriptionNumber of fixed DFE taps 3 , 7 Specifies the number of fixed DFE taps. Select thenumber of taps depending on the loss in y

Assign ToTX serial data.Syntaxset_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T <value> -to<tx_serial_data pin name>XCVR_A

Value DescriptionFIR_POST_2T_NEG Negative post-tap 2Assign ToTX serial data.Syntaxset_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP

DescriptionControls the magnitude of the second pre-tap for pre-emphasis. The default value is 0.Table 8-22: Available OptionsValue Description0 – 7 M

Related InformationArria 10 Pre-Emphasis and Output Swing SettingsXCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAPPin planner or Assignment Editor Name

Table 8-25: Available OptionsValue Description0 – 31 Magnitude 0 – 31Note: Refer to Arria 10 Pre-Emphasis and Output Swing Settings spreadsheet for se

I/O Standard ValueLVPECL TRISTATE_ON/TRISTATE_OFFLVDS TRISTATE_ON/TRISTATE_OFFAssign ToReference clock pin.Syntaxset_instance_assignment -name XCVR_A1

Document Revision History for Current Release92015.05.11UG-01143SubscribeSend FeedbackThis section provides the revision history for the chapters in t

Chapter Document Version Changes Made• Changed the bit to calibrate the fPLLand changed "Avalon-MM interface" to"internal configuration

Chapter Document Version Changes MadeInterlaken 2015.05.11 Made the following changes:• Added available preset variations to the"Interlaken"

Chapter Document Version Changes MadePCI Express (PIPE) 2015.05.11 Made the following changes:• Updated the "Transceiver ChannelDatapath for PIPE

Transceiver Channel Calibration Registers...7-3Fractional PLL Calibrati

Parameters Value DescriptionEnable rx_is_lockedtoref portOn/Off Enables the optional rx_is_lockedtoref status output port.This signal indicates that t

Chapter Document Version Changes MadeOther Protocols 2015.05.11 Made the following changes:• Updated the "Connection Guidelines fora PCS Direct P

Chapter Document Version Changes Made• Updated the figure for TransceiverNative PHY IP Core Parameter Editor.• PMA parameters• Updated the PMA paramet

Chapter Document Version Changes Made• Enhanced PCS Parameters• Removed the Enable rx_enh_fifo_cnt port and Enable tx_enh_fifo_cnt port parameters.• R

Chapter Document Version Changes Made• Dynamic Reconfiguration Parameters• Changed the table name from"Embedded Debug" to "OptionalReco

Chapter Document Version Changes Made• Enhanced PCS Ports• Deleted ports tx_enh_fifo_cnt andrx_enh_fifo_cnt from "EnhancedPCS TX and RX FIFO"

Chapter Document Version Changes MadePMA Architecture 2015.05.11 Made the following changes:• Updated link to XCVR_A10_RX_TERM_SEL in the "Transm

Chapter Document Version Changes MadeReconfiguration Interfaceand Dynamic Reconfigura‐tion2015.05.11 Made the following changes:• Completely revised,

Document Revision History for Previous ReleasesTable 9-1: Document Revision HistoryChapter DocumentVersionChanges MadeArria 10 TransceiverPHY Overview

Chapter DocumentVersionChanges MadeInterlaken 2014.12.15 Made the following changes to the parameter tables:• Added another value to the "TX chan

Chapter DocumentVersionChanges Made10GBASE-KR PHYIP with FEC Option2014.12.15 Made the following changes:• Changed the "10GBASE-KR PHY IP Core Bl

Parameter Range DescriptionFPGA fabric /Enhanced PCSinterface width32 , 40 , 50 , 64 , 66 ,67Specifies the interface width between the Enhanced PCSand

Chapter DocumentVersionChanges MadeXAUI PHY IP Core 2014.12.15 Made the following changes:• Added a PMA width requirement in the "TransceiverCloc

Chapter DocumentVersionChanges MadePCI Express 2014.12.15• Added PIPE Gen3 32 bit PCS Clock Rates table in the Gen3Rate Switchsection.• Updated the Ra

Chapter DocumentVersionChanges MadeOther Protocols 2014.12.15 Made the following changes:Using the "Basic (Enhanced PCS)" and "Basic wi

Chapter DocumentVersionChanges MadeResetting TransceiverChannels2014.12.15 Made the following changes:• Updated the "Transmitter Reset Sequence A

Chapter DocumentVersionChanges MadeReconfigurationInterface andDynamic Reconfigu‐ration2014.12.15 Made the following changes:• Re-organized the chapte

Table 9-2: Document Revision HistoryChapter DocumentVersionChanges MadeEthernet 2014.10.08 Changed the frequency for mgmt_clk in the "Avalon-MM I

Chapter DocumentVersionChanges MadeArria 10TransceiverProtocols andPHY IP Support2014.08.15 Made the following changes:• Updated table "Arria 10

Chapter DocumentVersionChanges MadeUsing the Arria 10Transceiver NativePHY IP2014.08.15 Made the following changes:• Updated references of MegaWizard

Chapter DocumentVersionChanges MadeInterlaken 2014.08.15 Made the following changes:• Changed parameter name in the "Signals and Ports of NativeP

Chapter DocumentVersionChanges Made• Specified the target BER of 10-12 in the 10GBASE-KR PHY IPCore section.• Removed the "Top Level Modules of t

Table 2-11: Enhanced PCS TX FIFO ParametersParameter Range DescriptionTX FIFO ModePhase-CompensationRegisterInterlakenBasicFast RegisterSpecifies one

Chapter DocumentVersionChanges Made• Updated the list of signals in the "Dynamic ReconfigurationInterface Signals" table.• Added new registe

Chapter DocumentVersionChanges MadePCI Express 2014.08.15 Made the following changes:• Added a new topic Pipe link equalization for Gen 3 data rate.•

Chapter DocumentVersionChanges MadeOther Protocols 2014.08.15 Made the following changes:• Changed references from MegaWizard to IP Catalog orParamete

Chapter DocumentVersionChanges Made• Changed the maximum data rate for GT channels to 28.3 Gbps.• Changed figure "Arria 10 PLLs and Clock Network

Chapter DocumentVersionChanges Made• Updated Using PLLs and Clock Networks section• Changed MegaWizard references to IP Catalog andParameter Editor.•

Chapter DocumentVersionChanges MadeArria 10Transceiver PHYArchitecture2014.08.15 Made the following changes• Arria 10 PMA Architecture• Added 2nd post

Chapter DocumentVersionChanges MadeReconfigurationInterface andDynamic Reconfi‐guration2014.08.15 Made the following changes:• Updated MegaWizard refe

Parameter Range DescriptionEnable tx_enh_fifo_pfull portOn / Off Enables the tx_enh_fifo_pfull port. This signalindicates when the TX FIFO reaches the

Parameter Range DescriptionEnable RX FIFOalignment worddeletion(Interlaken)On / Off When you turn on this option, all alignment words (syncwords), inc

Parameter Range DescriptionEnable rx_enh_fifo_align_clrport (Interlaken)On / Off Enables the rx_enh_fifo_align_clr input port. Only used forInterlaken

Parameter Range DescriptionEnable rx_enh_frame_lock portOn / Off Enables the rx_enh_frame_lock output port. When theInterlaken frame synchronizer is e

Parameter Range DescriptionEnable rx_enh_highber_clr_cntport(10GBASE-R)On / Off Enables the rx_enh_highber_clr_cnt input port. For the10GBASE-R transc

Parameter Range DescriptionEnable RXdescrambler(10GBASE-R/Interlaken)On / Off Enables the descrambler function. This option is available forBasic (Enh

Parameter Range DescriptionEnable RX databitslipOn / Off When you turn on this option, the Enhanced PCS RX blocksynchronizer operates in bitslip mode.

Arria 10 Transceiver PHY Overview12015.05.11UG-01143SubscribeSend FeedbackThis user guide provides details about the Arria® 10 transceiver physical (P

• Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations of Enhanced PCS onpage 2-279• Interlaken on page 2-76• 1

Table 2-24: TX and RX FIFO ParametersParameter Range DescriptionTX FIFO modelow_latencyregister_fifofast_registerSpecifies the Standard PCS TX FIFO mo

Table 2-25: Byte Serializer and Deserializer ParametersParameter Range DescriptionEnable TX byteserializerDisabledSerialize x2Serialize x4Specifies th

Parameter Range DescriptionRX rate matchinsert/delete +vepattern (hex)User-specified 20bit patternSpecifies the +ve (positive) disparity value for the

Parameter Range DescriptionNumber of wordalignment patterns toachieve sync0-255 Specifies the number of valid word alignment patterns thatmust be rece

Table 2-29: Bit Reversal and Polarity InversionParameter Range DescriptionEnable TX bitreversalOn / Off When you turn on this option, the 8B/10B Encod

Parameter Range DescriptionEnable rx_std_byterev_ena portOn / Off When you turn on this option and assert the rx_std_byterev_ena input control port, t

Parameter Range DescriptionEnable PCIepipe_rx_polarityportOn / Off When you turn on this option, the pipe_rx_polarity inputcontrol port is enabled. Yo

Parameter Value DescriptionEnable Altera DebugMaster EndpointOn/Off When you turn on this option, the Transceiver Native PHY IPincludes an embedded Al

Parameter Value DescriptionGenerate MIF(Memory Initializa‐tion File)On/Off When you turn on this option, the Transceiver Native PHY IPgenerates a MIF,

DeviceVariantStandard Power Mode (1), (2), (3)Reduced Power Mode (1), (2), (3)Chip-to-Chip Backplane Chip-to-Chip BackplaneGX(4)611 Mbps to 17.4 Gbps

Parameter Value DescriptionClear allprofiles- Clicking this button clears the Native PHY parameter settings for all the profiles.Refreshselectedprofil

Name Direction Clock Domain Descriptiontx_serial_clk1tx_serial_clk2tx_serial_clk3tx_serial_clk4Inputs ClocksThese are the serial clocks from the TX PL

Name Direction Clock Domain Descriptiontx_pma_rxfound[<n>-1:0]OutputSynchronous torx_coreclkin orrx_clkout basedon the configura‐tion.This port

Name Direction Clock Domain Descriptionrx_pma_clkslip Output Clock A rising edge on this signal causes the RX deserializerto slip the serial data by o

Table 2-39: Calibration Status PortsName Direction Clock Domain Descriptiontx_cal_busy[<n>-1:0] Output Asynchronous When asserted, indicates tha

Enhanced PCS PortsFigure 2-7: Enhanced PCS InterfacesThe labeled inputs and outputs to the PMA and PCS modules represent buses, not individual signals

Name Direction Clock Domain DescriptionYou must ground the data pins that are not active. Forsingle width configuration, the following bits are active

Name Direction Clock Domain Descriptionsync header is 2'b00 for a control word, and 2'b11 for adata word. For CRC32 error insertion, the wor

Name Direction Clock Domain Descriptionunused_rx_parallel_dataOutput rx_clkoutThis signal specifies the unused data when you turnon Enable simplified

Name Direction Clock Domain Descriptiontx_enh_fifo_pfull[<n>-1:0]Output Synchronous tothe clockdriving the writeside of the FIFO(tx_coreclkinor

Device Transceiver LayoutFigure 1-1: Arria 10 FPGA Architecture Block DiagramThe transceiver channels are placed on the left side periphery in most Ar

Name Direction Clock Domain Descriptionrx_enh_fifo_empty[<n>-1:0]Output Synchronous tothe clock drivingthe read side ofthe FIFO (rx_coreclkin or

Table 2-45: Interlaken Frame Generator, Synchronizer, and CRC32Name Direction ClockDomainDescriptiontx_enh_frame[<n>-1:0] Outputtx_clkout Assert

Name Direction ClockDomainDescriptionrx_enh_frame_diag_status[2<n>-1:0]Output rx_clkout Drives the lane status message contained inthe framing l

Table 2-48: GearboxName Direction ClockDomainDescriptionrx_bitslip[<n>-1:0] Inputrx_clkout The rx_parallel_data slips 1 bit for everypositive ed

Enhanced PCS TX Control Port Bit EncodingsTable 2-50: Bit Encodings for InterlakenName Bit Functionality Descriptiontx_control[1:0] Synchronous header

Table 2-53: Bit Encodings for Basic Double Width ModeFor basic double width mode, the total word length is 66-bit with 128-bit data and 4-bit synchron

Enhanced PCS RX Control Port Bit EncodingsTable 2-55: Bit Encodings for InterlakenName Bit Functionality Descriptionrx_control[1:0]Synchronous header

Table 2-56: Bit Encodings for 10GBASE-R , 10GBASE-KR with FEC, and Basic KR FECName Bit Functionalityrx_control[0] XGMII control signal for parallel_d

Table 2-58: Bit Encodings for Basic Double Width ModeFor basic double width mode, total word length is 66-bit with 128-bit data, and 4-bit synchronous

Standard PCS PortsFigure 2-8: Transceiver Channel using the Standard PCS PortsStandard PCS ports will appear, if either one of the Transceiver Configu