Altera User Flash Memory Bedienungsanleitung Seite 1

Altera User Flash Memory (ALTUFM) IP Core User Guide2014.08.18UG-040105SubscribeSend FeedbackThe Altera User Flash Memory IP cores provide interface l

DescriptionConfiguration SettingTurn on this option if you want to generate a netlist for your third-partyEDA synthesis tool to estimate the timing an

DescriptionConfiguration SettingSelect Base mode to use 8-bit address and data.Select Extended mode to use16-bit address and data.Configuration modeTu

Table 11: ALTUFM_I2C Parameter SettingsDescriptionConfiguration SettingYou can select from the following options: Create a new custom IP corevariation

DescriptionConfiguration Setting• Select Initialize blank memory if you do not want to specify any initial-ization file. Select Initialize from hex or

DescriptionConfiguration SettingSpecify the device family that you want to use.Which device family will you beusing?You can choose AHDL(.tdf), VHDL(.v

DescriptionConfiguration SettingSpecify the types of files to be generated. The Variation file (<function name>.v) contains wrapper code in the

DescriptionRequiredTypeParameter NameIdentifies the library of parameterized modules(LPM) entity name in VHDL Design Files (.vhd).NoStringLPM_TYPENote

DescriptionRequiredTypeParameter NameSpecifies the oscillator frequency for the user flashmemory. This parameter is used for simulationpurposes only.

DescriptionRequiredTypeParameter NameSpecifies whether the write-protect port protectsonly the upper half of the UFM block or the entireUFM block from

C**Functional Description ###func_descript###This chapter describes the functional description and the design examples of the ALTUFM IP core. Thissect

Resource Utilization and PerformanceThe ALTUFM IP core is only available for MAX II and MAX V devices. Resource usage is reported withdifferent interf

2. To simultaneously upgrade all IP cores that support automatic upgrade, click Perform AutomaticUpgrade. The Status and Version columns update when u

for Altera IP cores. Altera does not verify compilation for IP cores older than theprevious two releases.Related InformationAltera IP Release NotesMig

Related InformationAltera IP Release NotesFunctional DescriptionThis chapter describes the functional description and the design examples of the ALTUF

Table 19: Memory OrganizationAddress RangeSector1FFh100h10FFh000h0Using and Accessing UFM StorageUse the UFM to store data of different memory sizes a

• EraseThe UFM block supports byte write, but does not support byte erase, requiring a sector-based erase sequenceprior to any programming or writing.

Asserting READ, WRITE, and ERASE at the same time is not allowed. Multiple requests are ignored andnothing is read from, written to, or erased in the

In this example, you perform the following activities:• Create user flash memory with an SPI interface using the ALTUFM IP core and the parameter edit

ValueConfiguration SettingTurned offInstantiation template fileTurned onVerilog HDL black-box fileTurned offAHDL Include fileTurned offVHDL component

Figure 8: Simulation WaveformFunctional Results—Simulate the User Flash Memory in ModelSim-Altera SoftwareSimulate the design in the ModelSim-Altera s

Figure 9: ModelSim-Altera Software Simulation WaveformsALTUFM_PARALLEL PortsInput PortsTable 22: ALTUFM_PARALLEL Input PortsCommentsDescriptionRequire

Memory size is available only for the I2C interface where the size of the memory to be protected isspecified. This option is valid only when the acces

Output PortsTable 23: ALTUFM_PARALLEL Output PortsCommentsDescriptionRequiredPort Name(1)Data output.Yesdata_valid(1)Busy signal.YesnbusyOutput port [

ALTUFM_I2C PortsInput PortsTable 26: ALTUFM_I2C Input PortsCommentsDescriptionRequiredPort Name(1)Input port that specifies theLSB (bit 0) of the 7-bi

CommentsDescriptionRequiredPort NameData input from masterand data output fromslave.Bidirectional clock port.YessdaALTUFM_NONE PortsInput PortsTable 2

CommentsDescriptionRequiredPort Name(1)Data register output.YesdrdoutIf the osc port isspecified, the oscenaport is required. (1)Oscillator output.Noo

Table 8: ALTUFM_I2C Resource Usage (Read/write access with No erase)UFM BlocksWrite ProtectionAccess Mode Memory SizeHalf MemoryWriteProtectedFull Mem

IP Catalog and Parameter Editor (replaces MegaWizard Plug-In Manager)The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you e

the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, refer to Creatinga System with Qsys in the Quartus II Handbook.Relate

Specifying IP Core Parameters and Options (Legacy Parameter Editors)The Quartus II software version 14.0 and previous uses a legacy version of the par

Figure 5: IP Core Generated FilesNotes:1. If supported and enabled for your IP variation2. If functional simulation models are generated<Project Di

DescriptionConfiguration SettingYou can choose AHDL(.tdf), VHDL(.vhd), or Verilog HDL (.v) as the outputfile type.Which type of output file doyou want