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Altera Unique Chip ID IP Core User Guide

2014.09.02

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The Altera Unique Chip ID (ALTCHIP_ID) IP core allows you to uniquely identify the target FPGA before

device programming. This protects your device from receiving unauthorized programming data. Use the

IP Catalog and parameter editor to customize and generate the ALTCHIP_ID IP core.

The chip ID block has a 64 bit unique ID per die. The unique chip ID is read out from a 90 bit circular shift

concatenation of various fuse bits set during the manufacturing flow; these bits have Altera reserved values.

The Unique Chip ID register is implemented as a barrel shift register. For more information about customizing

IP cores.

This IP core is not supported for Arria 10 designs.Note:

Related Information

• Introduction to Altera IP Cores

• Altera IP Release Notes

Functional Description

At the initial state, the data_valid signal is low because no data is read from the chip ID block. After feeding

a clock signal to the clkin input port, the ALTCHIP_ID IP core begins to acquire the unique chip ID via

the chip ID block. After acquiring the unique chip ID, the IP core asserts the data_valid signal to indicate

that the unique chip ID value at the output port is ready for retrieval.

The operation repeats only when you provide another clock signal while the data_valid signal is low. If

the data_valid signal is high when you provide another clock signal, the operation stops because the

chip_id[63..0] output holds the chip ID.

A minimum of 67 clock cycles are required for the data_valid signal to go high.

The chip_id [63:0]output port holds the value of the unique chip ID until you reconfigure the device or

reset the IP core.

Installing and Licensing IP Cores

The Altera IP Library provides many useful IP core functions for production use without purchasing an

additional license. You can evaluate any Altera IP core in simulation and compilation in the Quartus II

software using the OpenCore evaluation feature. Some Altera IP cores, such as MegaCore

functions, require

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www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes

no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly

agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published

information and before placing orders for products or services.

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Inhaltsverzeichnis

Seite 1 - Functional Description

Altera Unique Chip ID IP Core User Guide2014.09.02ug-altchipidSubscribeSend FeedbackThe Altera Unique Chip ID (ALTCHIP_ID) IP core allows you to uniqu

Seite 2 - Related Information

Figure 7: Simulation in Quartus II Design FlowPost-fit timingsimulation netlistPost-fit timingsimulation (3)Post-fit functionalsimulation netlistPost-

Seite 3 - Using the Parameter Editor

Table 2: ALTCHIP_ID PortsDescriptionSize (in Bit)I/OPortFeeds clock signal to the chip ID block. Themaximum supported frequency is 100 MHz.When you pr

Seite 4 - Send Feedback

ChangesVersionDate• Updated parameterization steps for legacy parameter editor.• Added note that this IP core does not support Arria 10 designs.2014.0

Seite 5 - Legacy parameter

that you purchase a separate license for production use. You can use the OpenCore Plus feature to evaluateIP that requires purchase of an additional l

Seite 6 - Upgrading IP Cores

Figure 2: Quartus II IP CatalogSearch and filter IP for your target deviceDouble-click to customize, right-click for informationThe IP Catalog is also

Seite 7

Figure 3: IP Parameter EditorsView IP portand parameterdetailsApply preset parameters forspecific applicationsSpecify your IP variation nameand target

Seite 8

Specifying IP Core Parameters and Options (Legacy Parameter Editors)The Quartus II software version 14.0 and previous uses a legacy version of the par

Seite 9

Figure 5: IP Core Generated FilesNotes:1. If supported and enabled for your IP variation2. If functional simulation models are generated<Project Di

Seite 10 - ALTCHIP_ID

Corrective ActionIP Core StatusUpgrade of the IP variation is not supported in the current version of the QuartusII software due to IP core end of lif

Seite 11 - Document Revision History

Example 1: Upgrading IP Cores at the Command LineYou can upgrade IP cores that support auto upgrade at the command line. IP cores that do notsupport a

Seite 12 - ChangesVersionDate

6. To regenerate the new IP variation for the new target device, click Generate. When generation is complete,click Close.7. Click Finish to complete m

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