Altera Stratix IV GT 100G Bedienungsanleitung Seite 55
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Chapter 6: Board Test System 6–33
Configuring the FPGA Using the Quartus II Programmer
October 2010 Altera Corporation Stratix IV GT 100G Development Kit User Guide
Disable ALL
Disables all of the outputs of the clock generator.
Read
Reads the register values and calculates the frequency based on these values.
Clear
Resets the device and puts it back in the factory default state.
Set New Frequency
The Set New Frequency control sets the desired frequency after this button is pressed.
Configuring the FPGA Using the Quartus II Programmer
You can use the Quartus II Programmer to configure the FPGA with a specific SRAM
Object File (.sof). Before configuring the FPGA, ensure that the Quartus II
Programmer and the USB-Blaster driver are installed on the host computer, the USB
cable is connected to the 100G development board, power to the board is on, and no
other applications that use the JTAG chain are running.
To configure the Stratix IV GT FPGA, perform the following steps:
1. Start the Quartus II Programmer.
2. Click Add File and select the path to the desired .sof.
3. Turn on the Program/Configure option for the added file.
4. Click Start to download the selected file to the FPGA. Configuration is complete
when the progress bar reaches 100%.
1 Using the Quartus II programmer to configure a device on the board causes other
JTAG-based applications such as the Board Test System and the Power Monitor to
loose their connection to the board. Restart those applications after configuration is
complete.
- User Guide 1
- Contents 3
- Additional Information 5
- 1. About This Kit 7
- Software 8
- Chapter 1: About This Kit 1–3 9
- 1–4 Chapter 1: About This Kit 10
- Kit Features 10
- 2. Getting Started 11
- References 12
- 3. Software Installation 13
- Note to Figure 3–2: 15
- 4. Development Board Setup 17
- 5. Board Update Portal 21
- 6. Board Test System 23
- Preparing the Board 25
- Running the Board Test System 25
- Using the Board Test System 26
- The Config Tab 27
- MAX II Registers 28
- The GPIO Tab 29
- User DIP Switches 30
- User LEDs 30
- Push Button Switches 30
- Ethernet 30
- The Flash Tab 31
- The SSRAM Tab 33
- Random Test 34
- Incrementing Test 34
- The DDR3 Tab 35
- Performance Indicators 36
- Error Control 36
- Data Type 36
- Read and Write Control 36
- The QDRII Tab 37
- The CFP Tab 39
- The SFPA Tab 42
- PMA Setting 43
- Data Pattern 43
- The SFPB Tab 44
- The QSFP Tab 46
- Interlaken Tab 49
- The Power Monitor 51
- General Information 52
- The Clock Control 53
- Clock Tabs 54
- Registers 54
- Frequency 54
- Disable ALL 55
- Set New Frequency 55
- CFI Flash Memory Map 57
- A–2 Appendix A 58
- Appendix A A–3 59
- ./restore.sh r 60
- Appendix A A–5 61
- A–6 Appendix A 62
- Info–2 Additional Information 64
- Typographic Conventions 64
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