Altera Stratix III Bedienungsanleitung PDF herunterladen (Seite 23)

Chapter 5: Power Measurement 5–5

Changing the Design Example

then

where

SUPPLY

is 1.1 V for the FPGA core and 2.5 V for FPGA I/O.

Voltage measurements on the DMM should increase as frequency and resource

utilization increases according to Table 5–2 and Table 5–3 on page 5–2.

Changing the Design Example

The development kit includes source code for the Stratix III power design example so

you can use it as a starting point for your own measurements.

The design example uses 20 stamp.v modules, each with 8 outputs, for a total of

160 output pins. It assigns the pins selected as outputs to the HSMC connectors J8 and

J18.

To change the number of outputs, modify the design example and assign the pins

appropriately.

1 Power should track linearly with frequency and percentage resources. If you observe

superlinear power measurements, some temperature issue may be the cause.

Equation 5–1.

PVIV

SUPPLY

SENSE

SUPPLY

SENSE

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Altera Stratix III Bedienungsanleitung Seite 23