Altera RapidIO MegaCore Function Bedienungsanleitung Seite 172
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7–10 Chapter 7: Testbenches
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
In the first part of this test, the bfm_drbell_master sends a Doorbell message one clock
cycle after the bfm_io_write_master sends a write request. Write requests are sent and
checked according to the test sequence described in “SWRITE Transactions” on
page 7–5, and Doorbell messages are sent and checked according to the test sequence
described in “Doorbell Transactions” on page 7–8. The additional hardware shown in
Figure 7–2 is used to compare the transaction order before and after transmission on
the RapidIO link. Each queue has 40 bits of FIFO data. In each queue, the current
entry is set to 0 for a write request and to 1 for a Doorbell message. The comparator
compares bit by bit, checking for an exact match.
In the second part of this test, the DUT asserts an invalid byteenable value on the I/O
slave port for a single NWRITE_R transaction, and then transmits 32 NWRITE_R
transactions with a target address set out of bounds. After the bfm_io_write_master
initiates the sequence of NWRITE_R transactions, the bfm_drbell_master generates
transactions as in “Doorbell Transactions” on page 7–8. Each Doorbell transaction is
sent to the DUT immediately following a different NWRITE_R transaction. In
addition to checking for data integrity and for transaction order preservation despite
the tracking complication of cancelled transactions, the testbench checks that the
I/O
Slave Interrupt
register reflects each cancelled transaction correctly.
Port-Write Transactions
To test port-writes, the test performs some basic configuration of the port-write
registers in the DUT and the sister_rio module. It then programs the DUT to transmit
port-write request packets to the sister_rio module. The port-writes are received by
the sister_rio module and retrieved by the test program.
The configuration enables the
Rx
packet
stored
interrupt in the sister_rio module.
With the interrupt enabled, the sister_rio module asserts the
sister_sys_mnt_s_irq
signal, which indicates that an interrupt is set in either the
Maintenance
Interrupt
register or the
Input/Output
Slave
Interrupt
register. Because this part of the
testbench is testing port writes, the assertion of
sister_sys_mnt_s_irq
means that a
Port-Write transaction has been received and that the payload can be retrieved. To
enable the interrupt, call the task
rw_addr_data
defined in the sister_bfm_cnt_master
module.
A write operation is performed by the task with the address
0x10084
and data
0x10
passed as parameters. In addition, the sister_rio module must be enabled to receive
Port-Write transactions from the DUT. The task is called with the address
0x10250
and
data
0x1
.
After the configuration is complete, the test performs the operations listed in
Table 7–5.
Table 7–5. Port-Write Test
Operation Action
Places data into the
TX_PORT_WRITE_BUFFER
Write incrementing payload to registers at
addresses
0x10210
to 0x
1024C
Indicates to the DUT that Port-Write data is ready
Write
DESTINATION_ID
=
0x55
or
0x5555
,
depending on the device ID width setting, and
PACKET_READY
=
0x1
to
0x10200
Waits for the sister_rio module to receive the port-write Monitor
sister_sys_mnt_s_irq
- User Guide 1
- RapidIO MegaCore Function 1
- Contents 3
- Contents v 5
- Chapter 5. Signals 6
- Chapter 6. Software Interface 6
- Chapter 7. Testbenches 6
- Releases 10
- RapidIO IP Core Features 10
- Features 11
- Device Family Support 12
- Note to Table 1–2: 13
- Interoperability Testing 14
- Note to Table 1–4: 16
- Notes to Table 1–7: 18
- Notes to Table 1–8: 19
- Installation and Licensing 20
- 2. Getting Started 23
- Simulating IP Cores 26
- Calibration Clock 27
- Transceiver Settings 28
- IV GX Variations 28
- External Transceiver PLL 29
- Specifying Constraints 30
- Variations 32
- Core Instances 34
- Mode Selection 37
- Transceiver Selection 38
- Baud Rate 39
- Reference Clock Frequency 39
- Receive Buffer Size 39
- Transmit Buffer Size 39
- Enable 16-Bit Device ID Width 40
- Destination ID Checking 40
- Maintenance Logical Layer 41
- Port Write Tx Enable 42
- Port Write Rx Enable 42
- Avalon-MM Master 43
- Avalon-MM Slave 43
- Doorbell Slave 43
- Device ID 44
- Vendor ID 44
- Revision ID 44
- Processing Element Features 45
- Switch Support 45
- Enable Switch Support 46
- Number of Ports 46
- Port Number 46
- Source Operation 46
- Destination Operation 46
- 4. Functional Description 47
- Interfaces 48
- Avalon System Clock 49
- Reference Clock 50
- Other Input Clocks 51
- Clock Domains 51
- Notes to Figure 4–2: 52
- Notes to Table 4–2: 52
- Reset for RapidIO IP Cores 53
- Reset Controller 54
- Clocking and Reset Structure 55
- Physical Layer 56
- Physical Layer Architecture 57
- Receiver Transceiver 58
- CRC Checking and Removal 58
- Transmitter Transceiver 59
- Physical Layer Receive Buffer 60
- Transport Layer 65
- Receiver 66
- Transaction ID Ranges 67
- Concentrator Register Module 69
- Maintenance Module 72
- Maintenance Register 74
- Maintenance Slave Processor 74
- Maintenance Master Processor 76
- Port-Write Processor 78
- Registers Location 81
- Transactions 82
- Notes to Table 4–8: 84
- Notes to Table 4–9: 85
- Note to Figure 4–22: 91
- Notes to Table 4–11: 95
- Notes to Table 4–12: 96
- Note to Table 4–13: 96
- Notes to Table 4–14: 97
- Doorbell Module Block Diagram 99
- Preserving Transaction Order 100
- Doorbell Message Generation 101
- Doorbell Message Reception 102
- Note to Figure 4–30: 103
- 29’hb4b5959 104
- CRC field is not removed 105
- Note to Table 4–15: 105
- Logical Layer Modules 106
- Protocol Violations 108
- Fatal Errors 108
- Maintenance Avalon-MM Slave 109
- Maintenance Avalon-MM Master 110
- Port-Write Reception Module 111
- Input/Output Avalon-MM Slave 111
- Input/Output Avalon-MM Master 112
- Note to Table 5–2: 115
- 5–2 Chapter 5: Signals 116
- Physical Layer Signals 116
- Multicast Event Signals 117
- Note to Table 5–6: 118
- Notes to Table 5–7: 118
- Chapter 5: Signals 5–5 119
- 5–6 Chapter 5: Signals 120
- Notes to Table 5–8: 121
- 5–8 Chapter 5: Signals 122
- Chapter 5: Signals 5–9 123
- Register-Related Signals 124
- Avalon-MM Interface Signals 124
- Chapter 5: Signals 5–11 125
- 4x variations 126
- 2x and 4x variations 126
- Chapter 5: Signals 5–13 127
- Note to Table 5–19: 128
- Notes to Table 5–20: 129
- 5–16 Chapter 5: Signals 130
- Notes to Table 5–21: 131
- 5–18 Chapter 5: Signals 132
- 6. Software Interface 133
- Physical Layer Registers 136
- Note to Table 6–10: 141
- Note to Table 6–11: 143
- Note to Table 6–12: 143
- Note to Table 6–13: 144
- Note to Table 6–14: 144
- Note to Table 6–15: 144
- Note to Table 6–16: 145
- Note to Table 6–17: 145
- Notes to Table 6–18: 146
- Notes to Table 6–19: 147
- Note to Table 6–22: 148
- Note to Table 6–23: 148
- Note to Table 6–24: 148
- Receive Maintenance Registers 149
- Transmit Port-Write Registers 150
- Receive Port-Write Registers 151
- Note to Table 6–45: 154
- Note to Table 6–51: 156
- Doorbell Message Registers 158
- Note to Table 6–63: 160
- 7. Testbenches 163
- 7–2 Chapter 7: Testbenches 164
- Chapter 7: Testbenches 7–3 165
- 7–4 Chapter 7: Testbenches 166
- SWRITE Transactions 167
- NWRITE_R Transactions 168
- NWRITE Transactions 169
- NREAD Transactions 170
- Doorbell Transactions 170
- Chapter 7: Testbenches 7–9 171
- Port-Write Transactions 172
- Chapter 7: Testbenches 7–11 173
- 7–12 Chapter 7: Testbenches 174
- 8. Qsys Design Example 175
- Running Qsys 177
- Adding the Master I/O BFM 181
- Adding the On-Chip Memory 182
- Connecting Unconnected Clocks 183
- Connecting System Components 183
- Generating the System 185
- Simulating the System 186
- A. Initialization Sequence 187
- Additional Information 193
- Info–2 Additional Information 194
- Document Revision History 194
- Additional Information Info–3 195
- Info–4 Additional Information 196
- Note to Table: 197
- Typographic Conventions 198
- Info–6 Additional Information 198
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